Power Integrity

Power integrity covers all the issues associated with supplying low noise DC voltages to the active devices, and all the interconnects in the power distribution network (PDN) from the VRM to the on-die rail. This includes on-die capacitance, package lead inductance, on-package decoupling capacitors, multiple plane cavities, on-board decoupling capacitors, bulk decoupling capacitors, VRM design, parallel resonance structures and interactions in the entire PDN ecology.


Teledyne e2v, pSemi and GaN Systems unveil industry’s fastest HiRel GaN power solution at Satellite 2018

GaN Power solution features GaN FET and half-bridge driver for high-reliability applications

Teledyne e2v is launching a complete GaN power solution based on technology from pSemi (formerly Peregrine Semiconductor) and GaN Systems. The solution features GaN FETs and the industry’s first rad-tolerant, half-bridge power driver for GaN high-reliability applications. The technology will be demonstrated at Satellite 2018 March 12-15 in the Teledyne Defense Electronics booth (#619).

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Mitsubishi Electric US, Inc. to Exhibit at APEC 2018 in San Antonio, TX

Mitsubishi Electric US, Inc., Semiconductor and Device Division will exhibit for the first time at Applied Power Electronics Conference (APEC) in San Antonio, March 5-7, 2018.  The Semiconductor and Device Group will display its full lineup of power semiconductor products (formerly the Mitsubishi Products and Accessories Division of Powerex, Inc.) in booth #919.

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Santa Clara, CA

DesignCon 2018

Santa Clara, CA


Accurate and fast power integrity measurements

Measuring ripple, noise and transients on today’s low-voltage DC power rails challenges most oscilloscopes. With smaller rail voltages and 1 % to 2 % tolerances, instrument and probing noise make it hard to accurately measure specified tolerances. Adequate bandwidth is required to see harmonics of fast edges and higher frequency sources that can be coupled on power rails.

Cadence: Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing highspeed memory interfaces. This paper assesses how modern tools can be used to address poweraware SI challenges associated with I/O modeling, interconnect modeling, simulation, and analysis.

8 Ways to Overcome SI and PI Challenges

Keysight ADS 2016 features a host of new, technologies designed to improve productivity, including two electromagnetic (EM) software solutions specifically created to help signal and power integrity engineers improve high-speed link performance in PCB designs. What follows is a listing of 8 ways in which ADS 2016 can help you, the engineer, overcome your signal and power integrity challenges.

ANSYS-CPM model for Transient Analysis

Power Delivery Network(PDN) time domain noise analysis is an essential part for SI/PI/EMI analysis, SIwave can utilize CPM’s current PWL file as a current sink for transient analysis combed with C4 bump’s RLC parasitics to give more realistic and accurate noise value.