Power Integrity

Power integrity covers all the issues associated with supplying low noise DC voltages to the active devices, and all the interconnects in the power distribution network (PDN) from the VRM to the on-die rail. This includes on-die capacitance, package lead inductance, on-package decoupling capacitors, multiple plane cavities, on-board decoupling capacitors, bulk decoupling capacitors, VRM design, parallel resonance structures and interactions in the entire PDN ecology.

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  • Ta_designing-power-for-sensitive-circuits
    By Steve Sandler

    Designing Power for Sensitive Circuits

    How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.

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