Technical Articles

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The Goldilocks TDR

It pains me to say this, but there is such a thing as turning the TDR up too high and it is also easy not to have enough. If there is a “too high,” and a “not high enough,” there must also be a “just‐right,” or Goldilocks, setting. Using measurements, and a smattering of math, the Goldilocks setting answers
will be clear. Read on to find out how.


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Current Distribution, Resistance, and Inductance in Power Connectors

Engineers who design and model power distribution networks require accurate component level models from high frequency down to DC.  Accurate modelling of power connectors can guarantee best power transfer and minimize power-induced noise.  In this paper, which won a DesignCon 2020 Best Paper Award, the authors analyze the frequency-dependent resistance and inductance of various power connectors as well as pin patterns.


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Impulse Response from Insertion Loss

This article explains how to convert channel insertion loss data in a standard Touchstone file into the channel impulse response for time domain simulations. It also shows how some pre-processing of the Touchstone data can help improve results by eliminating the ringing that results from the use of frequency-limited measurement data. Read on to see how.


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Options for Copper Beyond 112 Gbps

Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?


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A Guide for Single-Ended to Mixed-Mode S-parameter Conversions

Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.


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A Simple Demonstration of Where Return Current Flows

This simple measurement demonstrates the most important principle in SI/PI and EMI: that the return current will flow in the path of lowest resistance below about 10 kHz. But above about 10 kHz, the return current will begin to redistribute in the return path to be adjacent to the signal conductor. Read on to learn more.


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Design for AMI: A New Integrated Workflow for Modeling 56G PAM4 SerDes Systems

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.


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