Incorporating the technique of using a quiet HIGH and quiet LOW I/O pin is a simple way of opening up a small window onto what is happening with the power rail of your die. Read on to have Eric Bogatin teach you how to implement it.
This DesignCon 2022 paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases from architectural definition, through analog and digital design, to design validation.
This DesignCon 2022 paper focuses on the use of models for overall system validation, including both system models that evaluate the end-to-end link performance, and models used for individual block functionality to validate a mixed-signal design.
In this article, Douglas Brooks and Johannes Adam illustrate how the thermal impacts of heated traces and pads are not limited to the board layer on which they exist; read on to see how they are reflected on every board layer above and below them.
In Donald Telian’s book he reveals his steps for successful serial links, called the “7 Steps to Successful Serial Links.” In this article, he discusses his most important steps: (one) minimize discontinuities, and (two) manage loss.
This article shows the impact of using one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method for accurately correlating signal integrity simulations to measurement.