Technical Articles

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PLL Characterization for Data Communication Components and Systems

Phase-locked loops (PLL) are used extensively throughout modern electronic systems. In data communication systems, PLLs are used in transmitter clock multipliers and receiver clock recovery circuits. A key performance factor for the PLL is how they manage jitter. A critical PLL metric is the jitter transfer function which is based on the PLL loop bandwidth. There are several measurement methods that can be used to characterize PLL loop bandwidth and jitter transfer. When operating on digital data signals, PLL bandwidth can vary with the data pattern. In this article, Greg Le Cheminant, Keysight Technologies, focuses on test methods that allow operation on data rather than only clock signals provide very high precision and useful insights into PLL behavior.


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Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32dB at 16GHz to -36dB at 32GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.


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What is This Material Called FR-4?

Within the PCB industry, FR-4 materials have long been accepted as “standard” materials. However, their use was not specific to the types of board being designed. For today’s high-speed, high-frequency designs, careful engineering and material selection relative to the resin systems and glass weave styles needed will ensure that a product will work as specified, as designed, and as manufactured. In addition, the finish of the copper used in the signal and power layers also needs to be controlled in order to ensure that loss goals are met.


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An Alternative Approach to Analyzing Far-End Crosstalk

Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.


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The Road from 1 Gbps-NRZ to 224 Gbps-PAM4

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.


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What is Enough? VDDQ Package Power Integrity Analysis With a DDR4 PHY

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 


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DesignCon Returns to Celebrate Engineers and Innovation

DesignCon, the premier high-speed communications and system design conference, returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits, January 30 to February 1, 2024. Group Event Director Suzanne Deffree reflects on the resources, networking, and innovation that DesignCon 2024 will bring.


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Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.


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VRM Modeling and Stability Analysis for the Power Integrity Engineer

DesignCon 2023 Paper

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.


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DDR5 Input Clock Jitter Tests

DDR5 Electrical and Timing Measurement Techniques

In this article, Randy White discusses variations in clock timing and how this can impact the reliability of a memory system. White highlights the importance of considering probe calibration, random jitter removal, and controlling bandwidth for accurate measurements, providing examples that demonstrate why care must be taken during probe attachment, calibration, and using a jitter/noise analysis application to evaluate jitter levels, therefore ensuring memory reliability.


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