Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC die

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. The traditional methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system level power distribution network (PDN) analysis is a chip die model, which requires specialized electronic design automation (EDA) tools to create. 

These EDA tools typically create chip models using either vector-based or vector-less dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use cases. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped, and partial. 

Here we explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. We also provide an improved methodology to determine if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC and/or shows a method of evaluating the PDN target impedance across a system.

Background

Power integrity plays a major role in the success or failure of all new electronic products. Power represents the major bottleneck in modern semiconductors and systems. Transistor scaling over the last two decades, as predicted by Moore’s law, has reached the integration of billions of transistors within an integrated circuit. 

With each generation of ASIC, node geometries continue to decrease resulting in lower gate capacitance which reduces power. However, this also creates more available area for additional transistors which overall leads to an increase of power [1]. Additionally, metal thickness and bump pitches are limiting the current carrying capabilities of the metal interconnect traces. Overall noise management is necessary due to increasing current density at faster edge rates and reduced voltage levels. Though, managing these limitations is a challenge that requires detailed evaluation and optimization. 

Traditional industry methods of evaluating power integrity for an ASIC die on a substrate generally lack sufficient accuracy. Many of these methods involve rule of thumb estimates for ASIC characteristics that do not effectively capture proper operation of a die on a substrate.

Proper power integrity analysis of a complex ASIC must encompass the entire PDN, including the interactions of the voltage regulator module (VRM), printed circuit board (PCB), package substrate, die, and decoupling capacitors at the package and PCB. An analysis that does not consider all noise sources and all states of operation could miss vital interactions that affect the entire PDN. Significant prior work has been demonstrated for the VRM and board, but substrate and die modeling requires additional tools and methods that are the focus of this paper.

ASIC designs today have thousands of bumps with multiple power domains demanding time-consuming analysis using EDA tools at the system level. The key element for system level PDN analysis is the chip die model which requires specialized EDA tools to create. These die modeling solutions can provide chip models with instantaneous current profiles based on either vector-based or vector-less dynamic power analysis. 

There are multiple challenges with generating vector-based chip models and these models do not always cover a complete ASIC die current profile. Die, substrate, and PCB system models have multiple possible configurations such as lumped, distributed, looped, and partial. 

This paper provides analysis using vector-less current profiles with lumped and looped models as opposed to analysis using distributed-partial models. This analysis shows the benefits of improved efficiency and accuracy, while reducing the overall risk to a given system PDN. Finally, this paper shows simulation to measurement correlation of a custom ASIC on a substrate as well as system level voltage ripple measurements.

This paper was presented at DesignCon 2022. Download the full PDF here.

References

[1] Swaminathan, M. S., & Engin, A. E. (2008). Power integrity modeling and design for semiconductors and systems. Prentice Hall.