Benjamin Dannan

Benjamin Dannan

Benjamin Dannan is a technical fellow and an experienced signal and power integrity (SI/PI) design engineer, advancing high-performance ASIC and FPGA designs at Northrop Grumman. He is a Keysight ADS Certified Expert with expert-level proficiency in high-speed simulation solutions and multiple 3D EM solutions. He has expert-level proficiency with multiple test and measurement solutions, including oscilloscopes, vector network analyzers (VNA), Time Domain Reflectometers (TDRs), function generators, and EMC lab testing equipment.

 

He is a senior member of IEEE, as well as a DesignCon TPC member with a multi-faceted background that includes a wide range of professional engineering and military experiences. His multiple years of engineering experience include designing, developing, and launching production products, ranging from ASICs, radars, fully autonomous robotic platforms, pan-tilt-zoom (PTZ) camera video systems, and ground combat vehicles. He is a specialist in signal and power integrity concepts, high-speed circuits, and multi-layered PCB design, as well as has multiple years of experience with EMC product development and certifications to support global product launches. Additionally, he has extensive experience with Chip-Package-PCB-VRM power delivery network (PDN) principles. 

 

Benjamin holds a certification in cybersecurity, has a BSEE from Purdue University, a Masters of Engineering in Electrical Engineering from The Pennsylvania State University, and graduated from the USAF Undergraduate Combat Systems Officer training school with an aeronautical rating. Benjamin is a trained Electronic Warfare Officer in the USAF with deployments on the EC-130J Commando Solo in Afghanistan and Iraq totaling 47 combat missions, as well as a trained USAF Cyber Operations Officer. In addition, he has co-authored multiple peer-reviewed journal publications and has received the prestigious DesignCon 2020 best paper award, given to authors leading as practitioners in semiconductor and electronic design.

ARTICLES

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The Challenge of Measuring a 40 µΩ (2000 Amp) PDN with a 2-Port Probe: The Measurement Result with Another VNA

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 


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What is Enough? VDDQ Package Power Integrity Analysis With a DDR4 PHY

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 


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VRM Modeling and Stability Analysis for the Power Integrity Engineer

DesignCon 2023 Paper

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.


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Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC die

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  



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