Steve Sandler

Steve Sandler

Steve Sandler has been involved with power system engineering for nearly 40 years. Steve is the founder of PICOTEST.com, a company specializing in power integrity solutions including measurement products, services, and training. He frequently lectures and leads workshops internationally on the topics of power, PDN, and distributed systems and is a Keysight certified expert for EDA software.

He frequently writes articles and books related to power supply and PDN performance and his latest book, Power Integrity: Measuring, Optimizing and Troubleshooting Power-Related Parameters in Electronics Systems, was published by McGraw-Hill in 2014. 

ARTICLES

Target Impedance Limitations and Rogue Wave Assessments on PDN Performance

A common design technique for power distribution networks (PDN) is the determination of the peak distribution bus impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. In theory, the allowable target impedance is determined by dividing the tolerable voltage excursion by the maximum change in load current.


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Bode Plots are Overrated

I’m not saying control loop stability isn’t important, of course it is. I am saying that whether your focus is power supply design, power integrity or mixed-signal, the Bode plot probably isn’t going to provide you with a reliable or optimum solution. Here are five major reasons for saying this...
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Designing Power for Sensitive Circuits

How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.


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Measuring Sub-milliOhm PDN Impedance

Measuring sub-milliOhms is difficult.  Getting low noise, sub-milliOhm measurements in very small circuits is a bit more difficult.  We recently had the opportunity to support R&D Altanova in performing this difficult measurement, here are some of the results.


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Designing Power for Sensitive Circuits

Low power, high performance circuits are often plagued by power supply related issues.  This common occurrence is frequently due to mythical (or misapplied) rules-of-thumb.  These rules of thumb often lead us in the wrong direction, making things worse rather than better.  In this article, I’ll highlight some of the most common mistakes engineers make and share some fundamental rules for designing clean power for sensitive circuits.  Applying these rules will result in higher performance, lower cost designs with fewer design iterations.


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Three stability assessment methods every engineer should know about

Many engineers are familiar with the Bode plot as an effective stability assessment method.  However, some authors suggest and even teach that the Bode plot is the only method needed.  This article shows why this thinking is short-sighted. A single, low cost instrument that can produce Bode plots, as well as two other stability assessment methods is discussed providing a more comprehensive stability assessment set of guidelines.


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PDN issues can occur in the simplest of circuits

When we think of PDN, the first images that usually come to mind are FPGA’s and CPU’s.  These circuit generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present.

This study focuses on a much smaller scale addressing a very simple circuit comprised the related PDN issue.  While the issues shown here may seem obvious to some, this is an excellent example of what is a very common problem.


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Two Common Power Delivery Network Measurement Issues

There are many questions about measuring Power Delivery Networks (PDN), but these two are very common ones.  Why do we calibrate the 2-port measurement with a 1Ω shunt resistor and why do I use DC blockers on both ports?  In this article I’ll provide responses to both of these questions.  The measurement setup in Figure 1 is an example where I used both the 1Ω calibration and the inclusion of the DC blockers.


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Evaluation of Gallium Nitride HEMTs for VRM Designs

As systems designers work hard to squeeze more and more features into less board space, the power delivery paths are becoming increasingly complex. The current mature VRM designs based on Silicon MOSFETs are hardly meeting present day requirements. One of the promising technologies touted to solve this conundrum of space and performance constraints is GaN HEMT. However, many engineers are hesitant to design very high frequency GaN VRMs from the ground up. This paper evaluates the steps required to modify existing Si-MOSFET designs for use with eGaN HEMT devices. The paper also compares the expected performance of GaN vs. Si in linear and switching regulator topologies and covers some of the measurement challenges as well.


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