Signal Integrity

Signal integrity covers all the issues about single ended and differential signal propagation from the transmitter to the receiver, including problems such as impedance control, discontinuities, reflections, topology, terminations, losses, ISI, jitter, eye diagrams, cross talk and ground bounce.


Samtec Releases Over 100,000 New Models on SnapEDA

Samtec is releasing new digital models for over 100,000 of its products on SnapEDA, the circuit board design library. With this new collaboration, designers can now easily discover, download, and design with over 100,000 ready-to-use Samtec connector models, helping accelerate the design process.

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Silicon Labs Introduces Industry’s Broadest Portfolio for 56G/112G SerDes Clocking

Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM4 SerDes and emerging 112G serial applications. With this portfolio expansion, Silicon Labs offers a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.

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New High-performance Oscilloscope From Rohde & Schwarz

Innovative Signal Integrity, Measurement Speed and Range of Functions

Rohde & Schwarz introduced the new high-performance R&S RTP oscilloscope. During the development of the new oscilloscope family, the focus was on measurement accuracy, speed, a wide range of functions and future-proof technology.

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Santa Clara, CA

DesignCon 2018

Santa Clara, CA


Power-Aware Analysis Solution

By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flows, and examining what is employed in Cadence® Sigrity™ power and signal simulations using the SPEED2000™, PowerSI®, Transistor-to-Behavioral Model Conversion (T2B™), and SystemSI™ tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also capable of creating and extracting signal and power analysis-required models and running design checks with power-aware constraints. Providing such a complete, or true, “power-aware solution” gives designers the confidence to produce high-quality designs.

Cadence: Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing highspeed memory interfaces. This paper assesses how modern tools can be used to address poweraware SI challenges associated with I/O modeling, interconnect modeling, simulation, and analysis.

Quick Start for Signal Integrity Design Using Keysight Advanced Design System (ADS)

A quick overview of how to download and use Signal Integrity Design Using Keysight Advanced Design System (ADS) including examples.

Using ADS for Signal Integrity Optimization

In the beginning there was transient simulation. Ensuring functional chip-to-chip links in a system meant performing a time-domain simulation with a SPICE simulator. The result was a time-domain waveform that was evaluated during post processing for signal integrity (SI). The main task was to measure the eye diagram, usually assuming a perfect clock as the phase reference. Due to rising signaling speeds and decreasing timing margins, the task was made more challenging when it became necessary to account for other effects.

PAM-4 Simulation to Measurement Validation with Commercially Available Software and Hardware

Next-generation of OIF and IEEE signaling standards are seriously considering PAM-4 signaling at 56 Gb/s over electrical channels. To exploit the advantages of PAM-4 signaling, a new measurement and simulation eco-system must be established and validated. Simulation of PAM-4 signals are done with an IBIS-AMI signal generator, an S-parameter channel model, and remote access software for receiver data recovery. Measured data is from commercially available PAM-4 generators, QSFP28 Ethernet cable assemblies, and digital oscilloscope receivers with specialized waveform processing. This paper will present correlation data to validate the software and hardware tools necessary for fast-track deployment in upcoming PAM-4 applications.

8 Ways to Overcome SI and PI Challenges

Keysight ADS 2016 features a host of new, technologies designed to improve productivity, including two electromagnetic (EM) software solutions specifically created to help signal and power integrity engineers improve high-speed link performance in PCB designs. What follows is a listing of 8 ways in which ADS 2016 can help you, the engineer, overcome your signal and power integrity challenges.

ANSYS-Near End and Far End Crosstalk Scanner

Crosstalk, or coupling, in high speed printed circuit board and packages represent one of main signal integrity design challenges. The cost of failure is very high and requires careful design strategies. This application note will introduce the capabilities for SIwave to automatically, and quickly, scan the entire PCB or package layout and report Near and Far End crosstalk coefficients

ANSYS-CPM model for Transient Analysis

Power Delivery Network(PDN) time domain noise analysis is an essential part for SI/PI/EMI analysis, SIwave can utilize CPM’s current PWL file as a current sink for transient analysis combed with C4 bump’s RLC parasitics to give more realistic and accurate noise value.