Gustavo Blando is a Senior Principal Engineer and leading Principal SI/PI Architect at Samtec Inc. In addition to his leadership roles, he's charged with the development of new SI/PI methodologies, high speed characterization, tools and modeling in general. Gustavo has twenty plus years of experience in Signal Integrity and high-speed circuits.
Gustavo Blando, a Samtec signal integrity architect, recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.
Engineers who design and model power distribution networks require accurate component level models from high frequency down to DC. Accurate modelling of power connectors can guarantee best power transfer and minimize power-induced noise. In this paper, which won a DesignCon 2020 Best Paper Award, the authors analyze the frequency-dependent resistance and inductance of various power connectors as well as pin patterns.
It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pro and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.
Glass-weave periodic loading can introduce additional insertion loss at midrange frequencies. This article characterizes these additional losses using actual glass weave cross-sectional data. It also shows how trace route angle and length can set up different secondary resonance patterns.
VNA measurements showed that the board-to-board skew distribution of realistic board topologies/routes can be broad, and the peak measured skew was quite significant. Post processing of TDR data suggested that long routes parallel to the board edge may be particularly susceptible to skew variation due to the glass weave.
As you know, "us", Signal and Power Integrity Engineers, are full of tricks, rules of thumb, and shortcuts. These tricks mostly help us understand something, save analysis time and, why not, make us look smarter than we really are!! In that vein, seldom have I encountered a quick and dirty trick as useful and underestimated as S-parameter renormalization.