Power Integrity

The Future of Power Integrity

Get six experts in a room together and you are likely to hear seven different opinions. Not so at the Future of Power Integrity Panel Discussion at DesignCon 2019.  The consensus of this panel of experts is that the future of power integrity will include single processor chips drawing as much as 1000 A and more. Read on for the details of this discussion!


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Avoid These Two Artifacts When Measuring SMPS Power Rails

Switch-mode power supplies (SMPS) are commonly used DC-to-DC converters in many electronic components. By their nature, they can generate a lot of radiated emissions. Unless care is taken, it is difficult to separate what is the actual voltage on the power rail and what is an artifact due to the way we probe the circuit. The project outlined here shows how to avoid EMI pick-up and cable reflection noise.


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Executive Q&A: Steve Sandler, Founder of Picotest

Executive Q&A with Steve Sandler, Founder of Picotest. Steve Sandler has been involved with power system engineering for nearly 40 years, has been a supporter of SI Journal since its founding, and now sits on its editorial advisory board. Steve is the founder of PICOTEST.com, a company specializing in power integrity solutions including measurement products, services, and training.


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Power Electronics vs. Power Integrity

The power electronics engineer and the power integrity engineer share a common goal: provide the system with the correct voltages, currents, and noise characteristics to achieve the desired performance. Unfortunately, they do not share much else. They generally use different tools, vocabulary, and figures of merit. As a result, both sides lose.


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Target Impedance Is Not Enough

Target impedance has become a standard tool when designing a power distribution network (PDN). It establishes a limit to the highest impedance the power rail on the die should see looking into the PDN. If the PDN impedance stays below this limit, even the worst-case transient current from the die will generate an acceptably low rail voltage noise.


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Preamplifier Options for Reducing Cable-Braid Loop Error

When measuring low impedance with the two-port shunt-through configuration, we potentially create an error due to the resistance of cable braids.  This error can be reduced or eliminated by using appropriate preamplifiers. There are professional preamplifiers on the market that do a great job reducing the cable braid error.  If you want to experiment with your own circuit, this article will help you


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VRM Modeling: A Strategy to Survive the Collision of Three Worlds

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.


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