Istvan Novak

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. 

I often get questions from my fellow design engineers from around the world asking why we should or should not use S parameters or Z parameters for power distribution network (PDN) designs or validation.  The truth is, we should be familiar with both, because depending on our design and validation tools, one or the other may be better suited for the task. Read on to find out why.

Engineers who design and model power distribution networks require accurate component level models from high frequency down to DC.  Accurate modelling of power connectors can guarantee best power transfer and minimize power-induced noise.  In this paper, which won a DesignCon 2020 Best Paper Award, the authors analyze the frequency-dependent resistance and inductance of various power connectors as well as pin patterns.

Measuring small resistance values is not trivial, but since 1861, when Lord Kelvin invented the Kelvin bridge,¹ we at least have a solution for measuring very low DC resistances: the four-wire Kelvin connection (see Figure 1). We measure the resistance by sending a known current through the resistor and measure the voltage drop using separate wires.

My friend Steve Sandler pointed out a major hurdle we face in power distribution design: power engineers (who design power converters) and power integrity engineers (who design system bypassing-decoupling networks) use different vocabulary, techniques, and requirements. To understand a little better how we got here, I want to start with a prediction I heard sometime in the early 90s at one of the conference keynote speeches: “In 10 to 20 years, computers will look like hairy steamy golf balls.” 

When measuring low impedance with the two-port shunt-through configuration, we potentially create an error due to the resistance of cable braids.  This error can be reduced or eliminated by using appropriate preamplifiers. There are professional preamplifiers on the market that do a great job reducing the cable braid error.  If you want to experiment with your own circuit, this article will help you

Power conversion circuits with control loop(s) are everywhere in electronic systems. We must establish stability and performance metrics for control loops and their circuits. However, generally accepted metrics may not be good enough. Is a crossover frequency with 45 degrees of phase margin and 10 dB of gain margin enough? How can we relate phase margin to peaking in the impedance profile and transient noise requirements? This article aims to answer these and other questions.

We are usually not worried about having via stubs on power and ground planes and shapes. Does it mean they are completely harmless?  When it comes to potential damage to high-speed signals, power-via stubs can be almost equally as bad as signal-via stubs.  Here is how and why.

Power distribution networks (PDNs) delivering power to ICs in a system need to be thoroughly designed and analyzed in order to make sure any voltage fluctuation on the rail is within the tolerance of every IC connected to that rail.  As ICs on the rail draw power, they generate a voltage fluctuation on the rail.  The PDN must have the capacity to supply enough charge such that the resulting voltage drop is less than the maximum voltage drop each IC on the rail can tolerate.  If voltage fluctuations appear outside IC tolerance limits, a slew of problems can surface such as IC damage, failure, or reduced lifespan.