Signal Integrity

RSS

Optoelectronic industry designers have traditionally used discrete optical devices for transceiver designs. The process requires manual integration of discrete free-space optical components such as lasers, modulator, photo detectors, isolators, MUX/DE-MUX, lenses in the form of optical gold box sub-assemblies such as transmit optical sub-assembly (TOSA).

Ask any engineer how to reduce the cross talk between two signal traces and the most common answer will be to add a guard trace. This should be the last resort, not the first choice. Guard traces can often introduce more problems than they solve.  Find out why in this article.

Engineers invest tens to hundreds of thousands of dollars in signal integrity simulation software—the goal being to gain an accurate understanding of how signals are going to behave in the final product. But how do you do that early in the design process without reliable, verifiable electrical properties for the dielectrics incorporated into your design?

MEMS timing systems offer the biggest selection of configurable timing features for reducing size and power. In addition, there are MEMS timing systems with a programmable platform and rich features to improve performance and speed development as well as manufacturing time while reducing risk.

When starting a new project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately. 

What is special about a material like PTFE that gives it such a low Dk and Df, while an epoxy has such a high Dk and Df? It is all about the chemical structure of the molecules and how they interact. Understanding the connection between chemistry and electrical properties is the starting place to engineer optimized materials for high-speed interconnects.

Why does a low cost through-hole SMA have a lower bandwidth than a surface mount SMA? The answer will surprise you.

Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes.

Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.

Looking into advanced error code correction? Many techniques involve forward error correction. But what exactly is that and how does it relate to your design? Cathy Liu spells it out in this article.