Bert Simonovich

Bert Simonovich

Lambert (Bert) Simonovich graduated from Mohawk College of Applied Arts and Technology, Hamilton, Ontario Canada, as an Electronic Engineering Technologist. Over a 32-year career, working at Bell Northern Research/Nortel in Ottawa Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in high-speed signal integrity and backplane design. After leaving Nortel in 2009, he founded Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions as a consultant. He has authored several publications and holder of two US patents. In addition to being a senior member of IEEE, he currently serves as a member of DesignCon's Technical Program Committee, EDICon's Technical Advisory Committee and Signal Integrity Journal's Editorial Advisory Board. His current research interests include high-speed signal integrity, modeling and characterization of high-speed serial link architectures. His most notable modeling achievement is the development of the "Cannonball-Huray" conductor roughness model used in several electronic design automation (EDA) software tools. 


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Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness

Designing the right PCB stackup can make or break product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. Sometimes, however, the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer uses smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause a product to fail compliance. So, how is this determined before finalizing the stackup? Read on to find out.

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A Guide for Single-Ended to Mixed-Mode S-parameter Conversions

Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.

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What Happens When Stripline Signals Cross Split Power Planes

Many claim that for stripline, it is ok to cross a split power plane, so long as the other adjacent reference plane is solid. Some others claim if there is an adjacent solid reference plane, less than 5mils away under the split, crosstalk will be mitigated. Read on to see an investigation into what really happens when stripline signals cross split power planes.

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A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.

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