Signal Integrity

Signal Integrity IP Market To Reach USD 3.75 billion by 2033

Tue, 28 Apr 2026 00:00:00 -0400

The Signal Integrity IP market is quietly becoming one of the most influential enablers of next-generation electronics, particularly in the United States, where innovation in semiconductors, data centers, and AI hardware is accelerating at an unprecedented pace.

AI-Assisted HFSS Modeling For 100 GHz+ High-Speed Interconnect Design

Thu, 23 Apr 2026 00:00:00 -0400

Advanced Chip and Circuit Materials Introduces Negative and Near-zero CTE Materials

Mon, 20 Apr 2026 10:06:50 -0400

ACCM launched two new materials: Celeritas HM50 and Celeritas HM001.

The Role of Precision Timing in Enabling Higher Bandwidth Per Rack Without Compromising Signal Integrity or Efficiency

Mon, 20 Apr 2026 00:00:44 -0400

SIJ Publishes April 2026 Issue

Sat, 18 Apr 2026 00:00:59 -0400

Signal Integrity Journal, covering signal integrity, power integrity and EMC/EMI, has published its April 2026 issue. Don't miss out on the latest. Download now!

The Role of Copper Pour and Picket Fence vias in Digital Designs

Fri, 17 Apr 2026 00:00:00 -0400

Samtec Cable Assemblies Test 224 Gbps PAM4

Wed, 15 Apr 2026 08:26:38 -0400

Samtec, Inc. announced the release of the BE71A Bulls Eye^® Phase & Amplitude Stable Test Assembly.

ACCM Celeritas™ SF1600 Delivers Zero-Skew for PCIe 7, 224 Gbps and Beyond

Mon, 06 Apr 2026 12:55:19 -0400

Advanced Chip & Circuit Materials, Inc. (ACCM) introduced Celeritas SF1600, a laminate and prepreg material that eliminates fiber weave skew at its root.

Keysight Introduces 220 GHz Lightwave Component Analyser to Validate Next-Generation Optical Transceiver Technology

Fri, 13 Mar 2026 08:35:17 -0400

Keysight Technologies, Inc. introduced the N4378A Lightwave Component Analyser (LCA).

Keysight Expands Digital‑Layer Error Performance Validation for High‑Speed 1.6T Interconnects in AI Data Centres

Wed, 11 Mar 2026 13:23:28 -0400

Keysight Technologies, Inc. introduced the Functional Interconnect Test Solutions (FITS) portfolio and FITS-8CH, the suite’s first product.

Keysight Introduces PAM3 Signalling with New GDDR7 Transmitter Compliance Solution for Next-Generation Graphics Memory

Thu, 19 Feb 2026 10:38:48 -0500

Keysight has announced its new graphics double data rate 7 transmitter compliance solution, that accelerates validation of Joint Electron Device Engineering Council standards for graphics and AI applications.

Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs

Tue, 17 Feb 2026 15:37:35 -0500

Keysight has introduced 3D Interconnect Designer, a new addition to its EDA portfolio. The solution addresses the mounting complexity of designing 3D interconnects for high-chiplet and 3DIC advanced packages used in AI infrastructure and data center applications.

Fraunhofer IPMS Develops New 10G TSN Endpoint IP Core for Deterministic High-Speed Ethernet Networks

Tue, 17 Feb 2026 08:54:30 -0500

The Fraunhofer Institute for Photonic Microsystems addresses this challenge with a new 10G TSN endpoint IP Core, enabling deterministic real-time communication at data rates of up to 10 Gbit/s.

How to Simulate Uniform Transmission Lines at Low Frequencies

Wed, 11 Feb 2026 00:00:00 -0500

This article details the electromagnetic simulation of low frequencies in Ansys Electronics Desktop, focusing specifically on arbitrary length transmission lines and cables with uniform cross sections. It presents two-dimensional, quasi-static field and circuit solvers as an alternative simulation method, covering the simulation workflow while highlighting the differences and benefits of using this method as opposed to using predominant full-wave field solvers.

Keysight and Point2 Technology Collaborate to Advance Next-Generation AI Scale-Up Interconnects

Thu, 29 Jan 2026 13:03:19 -0500

The collaboration validates Point2 Technology’s innovative e-Tube™ multi-terabit interconnects using Keysight's high-speed digital test solutions, addressing critical power and bandwidth challenges in AI infrastructure

Material-Induced Skew in High-Speed Multilayer PCBs: Influences and Mitigation Strategies

Sat, 17 Jan 2026 00:00:00 -0500

Among various forms of signal degradation, skew is a key contributor to timing errors in systems operating at multi-gigabit data rates. An increasingly important factor at high speeds is material-induced skew due to local differences in dielectric constant arising from the PCB’s woven glass fabric reinforcement. This article aims to unpack the root causes of material-induced skew, particularly focusing on the glass weave effect, and explores mitigation techniques ranging from laminate selection to signal routing strategies.

The Imperfect Via: The Rough Truth Lurks Beneath the Surface

lsimonovich@lamsimenterprises.com — Sat, 10 Jan 2026 00:00:00 -0500

Bert Simonovich explains why material anisotropy is not solely responsible for contributing to Dkeff surrounding a via hole structure. The via barrel conductor roughness and resin content of the as-fabricated dielectric pressed thicknesses must be considered and adjusted before applying this heuristic method to calculate Dkxy.

Evolution of PCIe Beyond Gen7: PCIe Gen8

Sat, 13 Dec 2025 00:00:00 -0500

The PCIe standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. Follow along as Abhijit Wander explores how sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

Using Ultra-Broadband Baluns to Perform Differential S-Parameter Measurements Using Single-Ended 2-Port VNA

Tue, 09 Dec 2025 00:00:00 -0500

This article demonstrates accurate differential S-parameter measurements obtained from a single-ended 2-port VNA using ultra-broadband baluns and attenuators. This measurement system is a cost-effective alternative to purchasing a multi-port test set for a VNA.

High-Speed Digital Interface Characterization Requires New Test Approach

hiroshi.goto@anritsu.com — Thu, 20 Nov 2025 00:00:00 -0500

The increasing speeds of digital interfaces to meet the ever-growing data demands of modern society places stress on design engineers. A new test methodology for measuring intra-pair skew is necessary to verify high-speed interfaces such as PCI Express. The BERT-based setup uses a new method with dual transmitters to control the phase of signals within a differential pair, enabling granular measurement of intra-pair skew. This capability is crucial for understanding and mitigating the impact of skew on BER margins at high data rates such as 64 GT/s.

Seeing Through the Noise: Reliable Power Rail Measurements in High-Current AI Systems

Wed, 19 Nov 2025 00:00:00 -0500

In this article, power rail voltage measurement uncertainty is examined using several different probe configurations to monitor VCore measurements on a Picotest S2000 load stepper board. The results reveal measurement variations up to 27 mV — a level of uncertainty that can completely mask the performance improvements engineers are seeking from advanced VRM technologies. Read on to learn how engineers can trust their measurements when the uncertainty exceeds the performance gains they are trying to validate.

DE-CIX Frankfurt Connects Deutsche Glasfaser to the World's First 800 Gigabit Internet Exchange Port from Nokia

Tue, 11 Nov 2025 00:00:37 -0500

The 800G-ZR+ optics mark the next leap forward in network technology: double the data performance, higher efficiency, and lower energy consumption.

Skyworks Introduces New Programmable Bulk Acoustic Wave Clocks for 5G, 6G, and Data Center Applications

Mon, 10 Nov 2025 14:54:31 -0500

Anritsu Breaks Bandwidth Barrier with World's First 145 GHz O/E Calibration Module, Accelerating 1.6 T Data Center Evolution

Thu, 30 Oct 2025 14:07:47 -0400

Anritsu Company has launched the MN4765B-0140 O/E Reference Calibration Module, the world’s fastest and first traceable solution to support the testing demands of next-generation data centers and the explosive growth of AI and ML.

Electrical and Thermal Simulations of Electronics in the AI Age

Thu, 30 Oct 2025 00:00:00 -0400

This article discusses electrical and thermal co-simulation of multi-pin interconnects. Using Ansys Q3D and Icepak (2025R1), it highlights key practices such as parametrization, matrix reduction, and mesh settings to ensure accurate and efficient results with complex geometries.

Samtec Expands Offering of Slim, High-Density AcceleRate HD Array Connectors

Tue, 28 Oct 2025 16:32:00 -0400

AcceleRate HD slim, high-density array connectors now available with 16 mm stack heights and up to 400 total positions.

You Measured What? Four Must-Know Checks Before Trusting Your Trace S-Parameters

Mon, 27 Oct 2025 00:00:00 -0400

S-parameter data can reveal more than what it initially shows. This article presents four key insights that can be derived from your S-parameters, enabling smarter simulation and improving your signal integrity intuition.

Superconducting Interconnect: The Effect of Kinetic Inductance on Signal Integrity

haider.clifton@mayo.edu — Wed, 22 Oct 2025 00:00:00 -0400

While the lossless characteristics of superconducting interconnect can trigger visions of tremendous bandwidths over infinite physical distances, superconductors have unique properties that can appreciably affect signal integrity in unexpected ways. This article introduces kinetic inductance from the eyes of signal integrity with the aim of preparing engineers to analyze superconducting links.

ManyPoint Networks: A System Co-Design Framework for 448 Gbps AI Fabrics and Beyond

Sun, 19 Oct 2025 00:00:00 -0400

This article introduces a hardware-centric definition of compute cluster bisection bandwidth as a performance metric for AI-scale 448 Gbps systems. Unlike traditional abstractions, this metric is grounded in physical interconnect layout and IO port availability, enabling system architects to evaluate bandwidth provisioning through real, bidirectional link paths.

Samtec Launches 800-Position AcceleRate HP High-Performance Array Connectors

Wed, 24 Sep 2025 00:00:48 -0400

Samtec announces the expansion of its AcceleRate® HP product line with the release of 800-position APM6 and APF6 high-performance array connectors available in a low-profile 5 mm stack height.