Dr. Hsinho Wu is a design engineer at Intel Corporation’s Programmable Solutions Group (formerly Altera). He presently works on high-speed communication systems of FPGA products. His development and research interests include signal integrity, clock and data recovery, equalizations, device and system modeling, simulation techniques, and software architecture.
What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.