Signal Integrity

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Ensuring High Signal Quality in PCIe Gen3 Channels

The increased data rates of today’s high-speed Input/Output (I/O) buses make maintaining transmission channel signal quality all the more challenging. One reason for the challenge is the parasitic effects that result from bus interconnects. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase—from 1 Gbps to 25 Gbps and beyond—to meet the ever increasing demand for more I/O bandwidth from modern networking applications and high-capacity storage.


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IEEE P370 Plug and Play Test Coupons boards

IEEE P370 Working Group Update

The IEEE P370 Working Group is focused on improving high-speed PCB measurements, specifically their project is the “Electrical Characterization of Printed Circuit Board and Related Interconnects at Frequencies up to 50 GHz.” If you weren’t able to make the IEEE P370 working group briefing at DesignCon 2017, here’s a summary of what was discussed.
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A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness

Presented at DesignCon 2017

In the GB/s regime, accurate modeling of conductor loss and phase delay is a precursor to successful high-speed serial link designs. In this paper, a practical method to model effective permittivity and phase delay, due to conductor surface roughness, is presented. By obtaining the dielectric and roughness parameters, solely from manufacturers’ data sheets, phase delay and effective permittivity can now be easily predicted. Detailed case studies and several examples test the model`s accuracy.


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Tektronix Delivers Automated 100G Electrical Test Solutions for DSA8300 Sampling Oscilloscopes

Tektronix, a leading worldwide provider of measurement solutions, today introduced new equivalent time automated compliance test solutions for 4-lane 100G electrical interfaces defined in the IEEE 802.3bm and 802.3bj specifications. The new capabilities along with the full set of Tektronix solutions for 100G and 400G characterization and validation will be demonstrated February 1-2 at DesignCon 2017, Booth 741.


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Anritsu BERT

Anritsu to Present Signal Integrity Testing Solutions, Technical Sessions at DesignCon 2017

Anritsu Co., a DesignCon 2017 Diamond Sponsor, will present testing solutions and technical sessions to aid engineers more efficiently develop next-generation chips, boards and systems used in emerging applications, including IoT/M2M and 5G, at DesignCon, beginning January 31 in Santa Clara, CA. Signal integrity solutions featuring the award-winning Signal Quality Analyzer (SQA) MP1800A BERT, as well as the VectorStar® and ShockLine™ vector network analyzers (VNAs) will be on display in the Anritsu booth (#633) throughout the show.


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