DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems. This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
Tektronix has expanded its line-up of PAM4 test solutions to include comprehensive 400G electrical compliance testing for OIF-CEI-56G VSR/MR/LR PAM4 standards. The new 400G-TXE software package runs on high-performance Tektronix DPO70000SX Real-Time Oscilloscopes; a lineup of models which go up to 70 GHz in bandwidth. The automated turnkey solution performs PAM4 compliance test sweeps in a single pass for shorter test times, more reliable and repeatable results, and greater ease of use.
Keysight is offering a free seminar to help high-speed digital design engineers, SI and PI engineers, and design team managers, learn the skills they need to overcome signal integrity (SI) and power integrity (PI) challenges.
Glass-weave periodic loading can introduce additional insertion loss at midrange frequencies. This article characterizes these additional losses using actual glass weave cross-sectional data. It also shows how trace route angle and length can set up different secondary resonance patterns.