Signal Integrity

16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory

The paper discusses the development of GDDR6 as a lower-risk and more cost-effective solution as compared to other high-bandwidth memory solutions.


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A Study of Forward Error Correction Codes for SAS Channels

This paper evaluates the performance of several choices of Reed-Solomon code and shows how a frame-interleaved RS(30,26) code can achieve 1e-15 bit-error rate (BER) in the presence of burst errors. See the authors conclude that, as data rates go higher, current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.


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Outer Loop Equalization for PCIe Cross-Lane Transceiver Optimization

PCIe Gen4 Standards Margin-Assisted Outer-Layer Equalization for Cross-Lane Optimization in a 16GT/s PCIe Link

PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.


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40 GHz PCB Interconnect Validation: Expectations vs Reality

What does it take to design PCB interconnects with good analysis-to-measurement correlation up to 40 GHz? Is it doable with typical low-cost PCB materials and fabrication process, typical trace width, via back-drilling and the shortage of space to place the stitching vias? This paper reports lessons learned from validation projects with the goal to build a formal procedure for systematic prediction of interconnect behavior up to 40 GHz. Topics include: selection of test structures, connectors and measurement equipment, and analysis uncertainties.

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A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.


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Samtec Releases Over 100,000 New Models on SnapEDA

Samtec is releasing new digital models for over 100,000 of its products on SnapEDA, the circuit board design library. With this new collaboration, designers can now easily discover, download, and design with over 100,000 ready-to-use Samtec connector models, helping accelerate the design process.


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