Signal Integrity

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DesignCon Returns to Celebrate Engineers and Innovation

DesignCon, the premier high-speed communications and system design conference, returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits, January 30 to February 1, 2024. Group Event Director Suzanne Deffree reflects on the resources, networking, and innovation that DesignCon 2024 will bring.


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Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.


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DDR5 Input Clock Jitter Tests

DDR5 Electrical and Timing Measurement Techniques

In this article, Randy White discusses variations in clock timing and how this can impact the reliability of a memory system. White highlights the importance of considering probe calibration, random jitter removal, and controlling bandwidth for accurate measurements, providing examples that demonstrate why care must be taken during probe attachment, calibration, and using a jitter/noise analysis application to evaluate jitter levels, therefore ensuring memory reliability.


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How to Optimize Probing and Signal Access for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s


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Fingerprint Your Serial Link to Solve SI

Signal Integrity, In Practice

Serial links have focused the practice of signal integrity on managing loss and discontinuities. Each system struggles with one or the other, making it imperative to determine which issue is dominant in your system and respond appropriately. This article by Donald Telian will explain how to characterize your link to help guide your thinking and your solution.


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Discontinuity Proximity Effect

Signal Integrity, In Practice

In this article, Donald Telian explains why discontinuities do not sum the same way as loss. Telian outlines that a failing an RL mask might indicate that Tx or Rx are simply too close to a discontinuity, causing the discontinuity proximity effect. Read on to learn more about how to to distance SerDes from discontinuities.


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Look Before You Leap

In this installation of Engineering Nightmares, Robert Haller explores a keystone rule to keep in mind when troubleshooting signal integrity problems. Learn why signal integrity engineers should never perform a measurement or simulation without first anticipating what they expect to see.



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Noise in Traffic: Signal Emulation for Automotive Apps

DesignCon 2023 Best Paper Award Winner

Automotive applications present new challenges to high-speed serial technology. Asymmetric, multi-gigabit signaling between sensors, processors, and displays in the unique noise environments of both electric and internal combustion engine vehicles create new problems for signal and power integrity engineers. This paper introduces the signal impairments required for receiver testing in the emerging automotive standards like ASA, MIPI's A-PHY, Automotive Ethernet, and more. Standards specify different sources of noise in different ways, some in the form of time evolutions, others as spectra. This paper focuses on techniques for generating and calibrating each noise source while describing advanced de-embedding techniques and addressing test equipment limitations.


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