We use cookies to provide you with a better experience. By continuing to browse the site you are agreeing to our use of cookies in accordance with our Cookie Policy.
Masashi Shimanouchi is a design engineer at Intel Corporation’s Programmable Solutions Group (formerly Altera). His work on high-speed serial links of FPGA products includes link system and component architecture, mathematical modeling, characterization, and link jitter and BER simulation tools development with expertise in signal processing, signal integrity and jitter area.
What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
