Technical Articles

Technical articles from companies and industry experts


Managing EMI and EMC at GHz and Beyond

Tools to Combat Radiated Emissions, for EMC Compliance and Performance Gains

New power-semiconductor technologies like SiC and GaN enable increased efficiency and higher switching frequencies, which allows smaller component sizes. But these gains come at the expense of greater radiated electromagnetic emissions, just as EMC regulations are getting tougher. How can engineers effectively minimize radiated EMI?

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DC Blocking Capacitor Location, who cares?

It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pros and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.

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Reducing EMI with Board-Level Shields

Reducing electromagnetic interference (EMI) is a key challenge when designing electronic devices. In this article, we will take a look into EMI challenges, the role of board-level shields (BLS) in reducing EMI, and the key criteria to keep in mind when selecting BLS.

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Addressing the 5G Challenge with Highly Integrated RFSoC

Radio transceiver, converters and FPGA on chip

The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications. Integration of ADC and DAC is not on its own sufficient to address the challenges.

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S-parameters: Signal Integrity Analysis in the Blink of an Eye

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.

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Ensuring High Signal Quality in PCIe Gen3 Channels

The increased data rates of today’s high-speed Input/Output (I/O) buses make maintaining transmission channel signal quality all the more challenging. One reason for the challenge is the parasitic effects that result from bus interconnects. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase—from 1 Gbps to 25 Gbps and beyond—to meet the ever increasing demand for more I/O bandwidth from modern networking applications and high-capacity storage.

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A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness

Presented at DesignCon 2017

In the GB/s regime, accurate modeling of conductor loss and phase delay is a precursor to successful high-speed serial link designs. In this paper, a practical method to model effective permittivity and phase delay, due to conductor surface roughness, is presented. By obtaining the dielectric and roughness parameters, solely from manufacturers’ data sheets, phase delay and effective permittivity can now be easily predicted. Detailed case studies and several examples test the model`s accuracy.

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