Technical Articles

Demystifying Edge Launch Connectors

A particularly challenging configuration is the edge launch, where connectors are used on the edge of the PCB with a transition to a microstrip trace. A poorly optimized connector footprint leads to degradation of the signal integrity performance, especially at high data rates. This paper identifies the root cause of the problem by showing how the electromagnetic fields behave at the transition area. Then it presents a design methodology, using simulated and measured data, that ensures the quality of high-speed data transmission.


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Avoid These Two Artifacts When Measuring SMPS Power Rails

Switch-mode power supplies (SMPS) are commonly used DC-to-DC converters in many electronic components. By their nature, they can generate a lot of radiated emissions. Unless care is taken, it is difficult to separate what is the actual voltage on the power rail and what is an artifact due to the way we probe the circuit. The project outlined here shows how to avoid EMI pick-up and cable reflection noise.


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Quick, Simple Way to Measure the System Bandwidth of a Scope-Probe System

While we get the scope’s bandwidth from the vendor, as soon as we add a cable, probe, or amplifier to the scope, we decrease the system bandwidth. The new system bandwidth is as important to know as the scope’s bandwidth, but it is generally difficult to measure except in a calibration lab. We offer a simple method of evaluating the transfer function and system bandwidth of any probing system using a wide band noise source. This method not only gives us information about the probes and interconnects, but it also tells us how the scope responds to the measurement system, information which cannot be measured by a VNA alone.


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Target Impedance Is Not Enough

Target impedance has become a standard tool when designing a power distribution network (PDN). It establishes a limit to the highest impedance the power rail on the die should see looking into the PDN. If the PDN impedance stays below this limit, even the worst-case transient current from the die will generate an acceptably low rail voltage noise.


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Preamplifier Options for Reducing Cable-Braid Loop Error

When measuring low impedance with the two-port shunt-through configuration, we potentially create an error due to the resistance of cable braids.  This error can be reduced or eliminated by using appropriate preamplifiers. There are professional preamplifiers on the market that do a great job reducing the cable braid error.  If you want to experiment with your own circuit, this article will help you


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16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory

The paper discusses the development of GDDR6 as a lower-risk and more cost-effective solution as compared to other high-bandwidth memory solutions.


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A Study of Forward Error Correction Codes for SAS Channels

This paper evaluates the performance of several choices of Reed-Solomon code and shows how a frame-interleaved RS(30,26) code can achieve 1e-15 bit-error rate (BER) in the presence of burst errors. See the authors conclude that, as data rates go higher, current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.


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VRM Modeling: A Strategy to Survive the Collision of Three Worlds

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.


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Outer Loop Equalization for PCIe Cross-Lane Transceiver Optimization

PCIe Gen4 Standards Margin-Assisted Outer-Layer Equalization for Cross-Lane Optimization in a 16GT/s PCIe Link

PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.


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