Technical Articles

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Overcoming Signal Integrity Channel Modeling Issues

In this article, John Baprawski reviews various issues when using S-parameter files to represent the channel in a SerDes system channel simulator. Stepping through several detailed examples, he demonstrates how paying close attention to the quality of the S-parameters allows you to have confidence in the derived SerDes design eye diagrams and other analysis methods. 


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Fixing Signal Integrity Issues in Software

In this article, Donald Telian shares an excerpt from his new book, “Signal Integrity, In Practice,” exploring how optimizing SES both fixes problems and improves system performance. He posits it’s crucial for hardware and SI engineers to understand how to optimize SES; read on to see why he attributes such importance to it. 


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224 Gbps Link Systems: Modulation vs. Channel vs. FEC

What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.


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Which Discontinuities are Small Enough to Ignore?

Understanding and minimizing discontinuities is increasingly important as serial links become both shorter and faster. Applying the old edge rate to roundtrip relationship to the modern era, Donald Telian in this article offers a rule-of-thumb to help gauge which interconnect structures, and hence discontinuities, to care about – and to what degree.  


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What to Expect in a Multi-Drop Bus

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.


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