HeeSoo LEE is a lead application developer for SI/PI/EM and SerDes product owner in the EEsof EDA Group of Keysight Technologies. He has held several different positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard including field applications engineer, consulting business manager, and marketing application engineer since 1989. Before he worked for Daeryung Ind, Inc. as a RF/MW circuit design engineer. He has 30 years of design and simulation experience in the area of RF, Microwave, and high-speed designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.
In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.
In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.
Here's a proposed method that improves the accuracy of DDR4 statistical simulation by using the mask correction factor. It presents a validated correlation between measured and simulated data to show that this methodology can be effectively used for DDR4 design