HeeSoo Lee is the DDR/SerDes product owner and an App Dev master scientist in the PathWave Software Solutions (PSS) group at Keysight Technologies. He has held several different positions since 1989 in Keysight/Agilent/Hewlett-Packard, including consulting business manager, technical marketing lead, and field applications engineer. Previously, he worked for Daeryung Ind. Inc. as a RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF, microwave, and high speed digital designs. He graduated with a BSEE degree from the Hankuk Aviation University, South Korea.
This article shows the impact of using one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method for accurately correlating signal integrity simulations to measurement.
Due to the ever increasing speed-grade of memory systems, it is necessary to apply equalizations, which creates severe burdens for memory system design engineers. Fortunately, the challenges have been overcome by an IBIS-AMI solution for single-ended signals and the introduction of a forwarded clocking solution. Read on to learn more.
In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.
In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.
Here's a proposed method that improves the accuracy of DDR4 statistical simulation by using the mask correction factor. It presents a validated correlation between measured and simulated data to show that this methodology can be effectively used for DDR4 design