High Speed Digital (HSD) transmit (Tx) and receive (Rx) circuits must be converted by signal integrity engineers to IBIS-AMI models, per the IBIS standard, to be used in SerDes channel simulators to evaluate their system margins. Oftentimes, the various commercial channel simulators in the market cost thousands of dollars for a yearly lease or to own. Modern SerDes channel simulation technology and the SerDes Tx/Rx modeling process has matured so that both are available for free using cloud-based tools at SerDesDesign.com. These tools provide the signal integrity engineer a low cost (zero-cost) path for modeling and simulating SerDes systems, custom modeling Tx/Rx designs, use of existing IBIS-AMI models, and converting their custom Tx/Rx designs into IBIS-AMI models.
This paper first gives an overview of modeling SerDes systems in a channel simulator, introduces the zero-cost tools available at SerDesDesign.com, then gives an example of simulating a SerDes system with Tx and Rx IBIS-AMI models.
Modeling Serdes Systems in Channel Simulators
SerDes systems are represented in channel simulators with SerDes channels and IBIS-AMI models per the IBIS Open Forum standard (currently at revision 7.1).
Figure 1 shows a typical SerDes system block diagram to be simulated using a channel simulator.
Figure 1. Typical SerDes System Representation in a channel simulator
This block diagram is generic for any channel simulator, but each tool has its specific way to represent this block diagram. This figure is referenced further in this paper.
The constituent parts of this SerDes system include the following.
- TX IBIS-AMI:
- This model typically contains a Tx equalizer often in the form of a feed-forward equalizer (FFE) with differential IBIS buffer output to the channel.
- The IBIS buffer can optionally be a 4-port S-parameter file.
- Tx package (Tx Pkg), Channel, Rx package (Rx Pkg):
- These pieces represent the differential channel.
- Each part is optional may be represented using S-parameter files.
- RX IBIS-AMI:
- This model typically contains an Rx continuous time equalizer (CTLE), a clock and data recovery unit (CDR), and decision feedback equalizer (DFE), with differential IBIS buffer input from the channel.
- The IBIS buffer can optionally be a 4-port S-parameter file.
A key channel simulator property to keep in mind is that it considers that the entire analog content, the green area in Figure 1 (the total channel) between the TX AMI portion and the RX AMI portion), is linear and time invariant (LTI). As an LTI system, the entire differential analog section in the SerDes system is accurately represented by its single ended impulse response. This key concept enables the channel simulator to achieve its fast simulation speeds.
The Zero-Cost Channel Simulator
There are many popular channel simulators (CS) in the market. They provide SerDes signal integrity (SI) engineers a valuable tool for evaluating their SerDes system designs for understanding how their systems perform under different conditions.
Oftentimes, an SI engineer might not have access to their company CS tool due to unavailable licenses or the need to time-share access to their tool with others in their company.
When the SI engineer needs to evaluate their Tx/Rx IBIS-AMI models under various test conditions with a given total channel, there is a zero-cost option available to use: the cloud-based SerDesDesign.com CS on the web.
The SerDes system CS is available here.
SerDesDesign.com also has CS support for repeater systems including an optical repeater system. Free user registration on the website is required to use the tools.
The SerDesign.com CS supports:
- NRZ and PAM-4 signaling.
- Tx/Rx parameterized behavioral models for FFEs and CTLEs.
- Generation of IBIS-AMI models from Tx/Rx behavioral models.
- Tx/Rx LTI and NLTV IBIS-AMI models (based on IBIS 7.0 or earlier).
- Tx/Rx jitter (based on IBIS 7.0 or earlier).
- IBIS corner cases: typical, min, max.
- AMI corner cases: typical, slow, fast.
- Use of S-parameters to represent Tx IBIS buffer, Tx package (Tx Pkg), Channel, Rx package (Rx Pkg), Rx IBIS buffer.
- Channel simulation Statistical mode.
- Channel simulation Bit-by-bit mode (100e9 bits/symbols supported).
- Channel simulation speed enhancement using multiple parallel processors.
- Display of resultant eye density plots, BER plots (timing and amplitude bathtub BER plots), BER extrapolation, BER contours, timing and amplitude PDF plots, and various eye metrics.
- Dedicated remote server allocated for user-only access and simulation.
The SerDesDesign.com CS has been used for over five years to model SerDes systems and create custom IBIS-AMI models for over 40 high speed SerDes semiconductor companies. Not all the features listed above are discussed in the following example SerDes systems.
Example PAM4 Serdes System Using Behavioral Models
The SerDes system discussed in this section is based on behavioral Tx/Rx models configured in the SerDesDesign tool. The models are used with PAM4 signaling at 12.5 GBaud.
The Tx behavioral model is an FFE with taps that can be automatically set for optimal eye opening during the model initialization. The Tx model has optional jitter associated with it.
The Rx behavioral model contains a CTLE, a CDR, and a DFE. The CTLE has 64 states defined with circuit time domain waveform data for each state. The CDR has parameterized characteristics including the observed jitter transfer function (OJTF) corner frequency. The OJTF is defined  as the phase response of a system which uses a PLL to generate its reference clock to detect the data bits being received. The OJTF has a high pass frequency response. Below the OJTF corner frequency (Fc), the input jitter is tracked and therefore is not observed at the output of the system. The DFE has taps that can be automatically and continuously adapted to achieve optimal output eye opening. The Rx model has optional jitter associated with it.
As described in Figure 1, the total channel includes the Tx model, Tx Pkg, channel, Rx Pkg, and Rx model. For the current SerDes system, each of these total channel blocks were represented with S-parameter files. The channel in the middle of the total channel had 16 dB loss at Nyquist (6.25 GHz).
Using the PAM4 data format, 12.5 GBaud, 32 samples per symbol, and 100,000 analysis symbols, the SerDes system was set up in the SerDes.com CS. During the simulation, the Tx and Rx model initialization process selects the Tx and Rx states for optimal eye opening before the Rx DFE. These optimal settings are displayed in the SerDes.com message window.
Once the SerDes system channel simulation has been successfully set up, many simulations may be run to evaluate the Tx/Rx models over their various states. After many successful simulations, the SerDes system is verified to meet requirements. The Tx/Rx behavioral models can optionally be converted into IBIS-AMI models.
Figure 2 shows the results for Test case 1: PAM-4 with Tx/Rx IBIS-AMI models and total channel.
Figure 2. Test case 1: PAM4; Tx + channel + Rx; SerDesDesign.com eye density plot (left) and timing waterfall BER plot (right)
As can be seen, the middle eye is about 66% open. The timing waterfall BER plot is zoomed in to the center 0.5 UI for better visibility of the curves. The BER curves show the raw (Monte-Carlo based) BER data (which goes down to 10^-6) along with the extrapolated BER data (which goes down to 10^-16). Plotting both BER data together shows how well the extrapolated BER tracks the raw BER.
The setup and use of the above SerDes system example is documented on the SerDesDesign.com website at Example_PAM4_SerDes.
The above test case is only a sample of the full featured Tx/Rx behavioral modeling and channel simulation capabilities available at SerDesDesign.com.
Example NRZ Serdes System Using TX/Rx IBIS-AMI Models
The SerDes system discussed in this section is based on Tx/Rx IBIS-AMI models developed for NXP Semiconductor Inc and Silicon Creations LLC. The models are usable with NRZ signaling with bit rates from 1 Gbps to 28 Gbps. For discussion in this paper, the bit rate is 25 Gbps and the SerDes.com CS is used.
The NXP Tx SerDes IP has this block diagram shown in Figure 3:
Figure 3. NXP Tx circuit design
This block diagram represents a 3-tap FFE and the circuit includes a signal path and control path with multiple filters, tap gains, on-die impedance structures facing the channel, and inherent in the design is a distributed nonlinearity. The circuit has three corner cases: typical, slow, and fast.
To create a behavioral model for this Tx circuit with three corner cases, the Tx circuit was treated as a black box with stimulus/response waveforms captured, from which the circuit model can be extracted. The Tx output IBIS buffer included the chip on-die impedance and was defined using S-parameters for each corner case. The FFE was defined with a swing level with 14 states, a pre-cursor with 25 states (12 negative, 0, 12 positive), and a post-cursor with 33 states (16 negative, 0, 16 positive) for each corner case. The IBIS-AMI modeling approach was based on collecting spice circuit simulation stimulus/response waveforms for a defined set of FFE states.
An example of waveforms collected for the typical corner case with the post code set to 11 and the pre-code swept from 0 to 12 is shown in Figure 4. The stimulus waveform was at a defined bit rate with NRZ signaling and a repeating pattern of 10 0’s and 10 1’s.
Figure 4. NXP Tx circuit waveforms collected
These response waveforms are at the Tx chip IBIS buffer output. The IBIS buffer characteristic is de-embedded from the response waveforms to obtain the AMI model characteristics. The AMI model converts the waveforms to a set of FFE tap gains, tap delays, and tap filtering for the specific bit rate and sample rate used in a simulation.
Thus, the combined Tx AMI model and Tx IBIS model provide the same characteristics as defined by the Tx circuit black box stimulus/response waveforms data.
The Silicon Creations Rx SerDes IP has this block diagram shown in Figure 5:
Figure 5. Silicon Creations Rx circuit design