Signal Integrity

Comparing Embedded Coplanar Waveguide and Stipline for Multi-Layer Boards

It is important in high-speed digital applications to decrease the form factor and increase signal density by reducing isolating metal layers, all while preserving comparable crosstalk, loss and dispersion at the frequency of interest. This paper takes a look at how you can do that by showing how coplanar waveguide with smaller form-factor outperforms stripline in isolation and coupling.


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IEEE P370: A Fixture Design and Data Quality Metric Standard for Interconnects up to 50 GHz

The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.


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Just how good are VNA Measurements?

Just because someone has a VNA capable of 60 GHz bandwidth doesn’t mean it will always give the same results. It is not the instrument, but the measurement procedure that seems to influence the quality of the measurements the most.  Read on for information on a recent study from Jason Ellison, Heidi Barnes, and Jose Moreira  as well as 7 tips for improving your measurements.


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PAM4: For Better and Worse

Is PAM4 worth the hassle?

That’s the question that will trigger your amygdala’s fight or flight response as you encounter the many annoyances that PAM4 brings to your world. Since you’re in a lab rather than a jungle, that fight or flight response might translate into sarcastic cracks like: “Right, that higher BER requirement makes it all so much easier—not.” “Good old NRZ, those were some fine bits. Remind me why I asked for this?” And, “dear NRZ, I never knew how much I loved you until I lost you.”


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PCI Express Gen5 is Coming: What You Need to Know for Tx Measurements

While we all love increased network speed, there is an implied assumption that the backbone speeds of the internet will keep up with this rising demand placed upon it by millions of new 5G devices. PCIe 5.0 (or Gen5) represents the technology that is needed by the computer, data center, and ultimately the 5G wireless industry to enable the next generation of mobile and desktop applications. So, what is PCI Express 5.0 and how does it compare to PCI 4.0? Read on to find out.


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Demystifying Edge Launch Connectors

A particularly challenging configuration is the edge launch, where connectors are used on the edge of the PCB with a transition to a microstrip trace. A poorly optimized connector footprint leads to degradation of the signal integrity performance, especially at high data rates. This paper identifies the root cause of the problem by showing how the electromagnetic fields behave at the transition area. Then it presents a design methodology, using simulated and measured data, that ensures the quality of high-speed data transmission.


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Test System Addresses Demands of 56/112G PAM4 Using Upcoming IEEE P370 Standard

eSilicon was in the Samtec booth at DesignCon 2019 presenting their collaboration with Wild River Technology to develop an advanced test system that addresses the difficult signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance.


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