Signal Integrity

A Brave New World: Simulating DDR5

Eagerly anticipated, the next generation of DRAM technologies (DDR5/LPDDR5) are presently being validated in the lab by leading silicon vendors worldwide. This latest generation has a big surprise in store for hardware engineers and SI specialists that need to simulate such systems. DDR5 will introduce decision feedback equalization (DFE) for the DRAM receiver for the very first time.


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Return Current Transition Between Planes

Return current for a signal always finds a way to flow as close to the signal as possible, thus minimizing the magnetic energy stored in the loop defined by the signal and its return path. So, the return current path is the combination of conduction paths that together minimize the stored magnetic energy. Some elements of the return current path may be part of the design and other elements may be unintentional.


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Modeling PCB Interconnects with Geometry and Material Parameters Variations for 56 Gbps Links

Measured S-parameters and cross-sections of PCB interconnects are used in this paper to identify the parameters of electrical models suitable for statistical analysis of interconnects with manufacturing variations. The constructed models reproduce observed effects of geometry and material properties variations on the loss, delay, and impedance, and they are suitable for yield analysis of interconnects with up to 56 Gbps signals.


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