Signal Integrity

Coming Up: Easier Signal Integrity Simulation Setup with IBIS 7.0

There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!


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Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and the Implications for COM

While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.


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Comparing Embedded Coplanar Waveguide and Stipline for Multi-Layer Boards

It is important in high-speed digital applications to decrease the form factor and increase signal density by reducing isolating metal layers, all while preserving comparable crosstalk, loss and dispersion at the frequency of interest. This paper takes a look at how you can do that by showing how coplanar waveguide with smaller form-factor outperforms stripline in isolation and coupling.


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IEEE P370: A Fixture Design and Data Quality Metric Standard for Interconnects up to 50 GHz

The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.


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