Uniform transmission lines are best suited for high-speed data transmission because of their broadband impedance characteristics. In some applications, a minor deviation from uniformity can help in optimizing other desired signal integrity metrics. This paper addresses some of the challenges involved with this approach.
Can common via structures transfer any data rate or are they limited with a defined bandwidth? If so, what limits its bandwidth? And what can be done when the bandwidth of the signal is greater than the bandwidth of the G-S-S-G structure? This technical feature from Dror Haviv explains.
Designers pushing the limits in their application can run into situations where the XO performance is inadequate for their next design due to the way it reacts to the noise and ripple in the power supply. To achieve optimal performance, they most likely will find they will need to do more than a simple datasheet evaluation to select their next XO. Read on for details on a PSNR test method to help select an optimal XO.
This article explains how to convert channel insertion loss data in a standard Touchstone file into the channel impulse response for time domain simulations. It also shows how some pre-processing of the Touchstone data can help improve results by eliminating the ringing that results from the use of frequency-limited measurement data. Read on to see how.
Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?
Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.
In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.