Signal Integrity

RSS

Keysight has announced its new graphics double data rate 7 transmitter compliance solution, that accelerates validation of Joint Electron Device Engineering Council standards for graphics and AI applications. 

Keysight has introduced 3D Interconnect Designer, a new addition to its EDA portfolio. The solution addresses the mounting complexity of designing 3D interconnects for high-chiplet and 3DIC advanced packages used in AI infrastructure and data center applications.

The Fraunhofer Institute for Photonic Microsystems addresses this challenge with a new 10G TSN endpoint IP Core, enabling deterministic real-time communication at data rates of up to 10 Gbit/s.

This article details the electromagnetic simulation of low frequencies in Ansys Electronics Desktop, focusing specifically on arbitrary length transmission lines and cables with uniform cross sections. It presents two-dimensional, quasi-static field and circuit solvers as an alternative simulation method, covering the simulation workflow while highlighting the differences and benefits of using this method as opposed to using predominant full-wave field solvers. 

The collaboration validates Point2 Technology’s innovative e-Tube™ multi-terabit interconnects using Keysight's high-speed digital test solutions, addressing critical power and bandwidth challenges in AI infrastructure
 

Among various forms of signal degradation, skew is a key contributor to timing errors in systems operating at multi-gigabit data rates. An increasingly important factor at high speeds is material-induced skew due to local differences in dielectric constant arising from the PCB’s woven glass fabric reinforcement. This article aims to unpack the root causes of material-induced skew, particularly focusing on the glass weave effect, and explores mitigation techniques ranging from laminate selection to signal routing strategies.

Bert Simonovich explains why material anisotropy is not solely responsible for contributing to Dkeff surrounding a via hole structure. The via barrel conductor roughness and resin content of the as-fabricated dielectric pressed thicknesses must be considered and adjusted before applying this heuristic method to calculate Dkxy.

The PCIe standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. Follow along as Abhijit Wander explores how sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

This article demonstrates accurate differential S-parameter measurements obtained from a single-ended 2-port VNA using ultra-broadband baluns and attenuators. This measurement system is a cost-effective alternative to purchasing a multi-port test set for a VNA. 

The increasing speeds of digital interfaces to meet the ever-growing data demands of modern society places stress on design engineers. A new test methodology for measuring intra-pair skew is necessary to verify high-speed interfaces such as PCI Express. The BERT-based setup uses a new method with dual transmitters to control the phase of signals within a differential pair, enabling granular measurement of intra-pair skew. This capability is crucial for understanding and mitigating the impact of skew on BER margins at high data rates such as 64 GT/s.