Signal Integrity

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Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.

In this article, Cathy Liu discusses how channel error models and FEC performance analysis have been updated according to industry changes, as well as how different Ethernet coding schemes have been studied and simulated for 800GE and 1.6GE systems with 200 Gbps per lane. Liu investigates concatenated FEC with soft-decision decoding for inner code to protect 200 Gbps optical link and the effect of different FEC options on system SI.

In just two generations, six different technological revolutions have transformed our economy, our careers, and our quality of life, for better or for worse. Eric Bogatin reflects upon industry progress and explores the potential impact of the latest development in technological innovation, generative AI.

DesignCon, the premier high-speed communications and system design conference, returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits, January 30 to February 1, 2024. Group Event Director Suzanne Deffree reflects on the resources, networking, and innovation that DesignCon 2024 will bring.

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.

In this article, Randy White discusses variations in clock timing and how this can impact the reliability of a memory system. White highlights the importance of considering probe calibration, random jitter removal, and controlling bandwidth for accurate measurements, providing examples that demonstrate why care must be taken during probe attachment, calibration, and using a jitter/noise analysis application to evaluate jitter levels, therefore ensuring memory reliability.

Samtec, Inc.’s Generate high-speed edge card sockets (HSEC6-DV Series) support 64 Gbps PAM4 (32 Gbps NRZ) applications and are PCIe 6.0 capable. 

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s

Serial links have focused the practice of signal integrity on managing loss and discontinuities. Each system struggles with one or the other, making it imperative to determine which issue is dominant in your system and respond appropriately. This article by Donald Telian will explain how to characterize your link to help guide your thinking and your solution.

In this article, Donald Telian explains why discontinuities do not sum the same way as loss. Telian outlines that a failing an RL mask might indicate that Tx or Rx are simply too close to a discontinuity, causing the discontinuity proximity effect. Read on to learn more about how to to distance SerDes from discontinuities.