ARTICLES

Dannan Cover 1-9-24.jpg

What is Enough? VDDQ Package Power Integrity Analysis With a DDR4 PHY

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 


Read More
f1  2631.jpg

Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC die

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  



Read More