Signal Integrity

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In this article, Tyler Huddleston explores causality in relation to signal and power integrity simulations. He reviews how causality affects time-domain simulation fidelity as well as how non-causal s-parameters can result from real measurements and simulations. Learn about how non-causal data can be avoided and the consequences of using a non-causal model in time-domain simulations.

The collaboration provides customers with extended product availability and supply flexibility to a portfolio of robust, scalable connectivity solutions for a wide range of high-performance applications demanding high signal integrity and density.

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.

This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.

Point2 Technology’s e-Tube offers a compelling alternative to copper cables and optics. It extends copper’s reliability and economics to support terabit-scale data rates in a lightweight, power-efficient, and highly manufacturable form to address short reach, AI cluster scale-up in data centers. With roadmap scalability to multi-terabit and compatibility with standard cable form factors, e-Tube redefines the compute fabric for next-generation AI clusters.

Anritsu announces that it has helped AMD accelerate the testing of electrical compliance for the PCI Express specification for pre-production AMD EPYC CPUs.

Skyworks introduces the SKY63104/5/6 family of jitter attenuating clocks and the SKY62101 ultra-low jitter clock generator.

Keysight's early access to PCIe CEM test tools enables AMD to reach 64 GT/s for next-generation server CPUs.