Signal Integrity

RSS

When I first started studying Maxwell’s Equations, I was always intrigued by its mathematical finesse. How could someone think of that? Today we take them for granted and we sometimes forget how amazing they are and what a genius the guy was. In my view, James Maxwell should be with, if not above, Einstein and Newton among the greatest physicists to ever live, but outside our field people seldom know who Maxwell was. 

Mentor, a Siemens business, today announced its new HyperLynx® printed circuit board (PCB) simulation technology for high-performance designs, now providing the industry’s first end-to-end fully automated serializer/deserializer (SerDes) channel validation solution.

No matter how well you understand the design principles, and no matter how much experience you have in designing boards, it’s easy for some problems to slip through the cracks because you just forgot to check that feature, or your design is just too big to manually check. This is where a design rule checker comes in.

DesignCon has been a tremendous source of information for myself and for the team I have been working with at SUN Microsystems, which later became part of Oracle Corporation. This summary is an attempt to capture some of the most influential papers from the past twenty years that made the biggest impact on our work.

It’s what you don’t know you don’t know that can ruin your day. This paper notes in detailed examples that with today’s high-speed designs, we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three disciplines and become educated about each of them to achieve successful designs.

A Unique Hands-on Opportunity to Characterize Interconnects to 50 GHz, sponsored by the IEEE P370 Standards group and Samtec.

Researchers at the National Institute of Standards and Technology (NIST) have invented a new approach to testing multilayered, three-dimensional computer chips that are now appearing in some of the latest consumer devices. The new method may be the answer the semiconductor industry needs to quickly assess the reliability of this relatively new chip construction model, which stacks layers of flat circuitry atop one another like floors in a building to help make chips ever-faster and packed with features.

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.