Signal Integrity

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The paper discusses the development of GDDR6 as a lower-risk and more cost-effective solution as compared to other high-bandwidth memory solutions.

Ken Willis provides some background on the IBIS AMI standard and looks ahead to what’s next.

Eric Bogatin explores just how much better the sine wave is from a more expensive function generator compared to the lower cost units. He asks the question: Just how much bang do you get for your buck? Read on to see how he does it.

If you are working on chip and package design, ground bounce is an important concern.  SIJ Technical Editor Eric Bogatin and his University of Colorado students share the results of a study in best design practices to minimize ground bounce noise.

This paper evaluates the performance of several choices of Reed-Solomon code and shows how a frame-interleaved RS(30,26) code can achieve 1e-15 bit-error rate (BER) in the presence of burst errors. See the authors conclude that, as data rates go higher, current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.

PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.

Microchip today announced the new dsPIC33CK Digital Signal Controller (DSC) with expanded context selected registers to reduce interrupt latency and new, faster instruction execution to accelerate Digital Signal Processor (DSP) routines.