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Signal Integrity

Enabling SI Engineers to Analyze Multi-Gigabit Serial Links and Memory Interfaces

December 17, 2018

Way back in 2007, EDA companies collaborated to drive an extension to the IBIS standard called the algorithmic modeling interface (AMI) to enable simulation of multi-gigabit serial link interfaces. This went hand-in-hand with channel (as opposed to traditional circuit) simulation, which enabled many bits of traffic to be simulated. The data rates back then were typically in the 2.5 to 5Gbps range—right about where DDR4 and DDR5 sit today.

A couple of things drove that original need for channel simulation and AMI in serial links. One was the requirement to analyze eye diagrams vs. a mask (i.e., waveform keepout area) at a particular bit error rate (BER). It wasn’t practical to simulate empirically to determine BER (simulating 1e16 bits still isn’t practical today), so it was necessary to extrapolate statistically to calculate BER. But to do that reliably, one must start with a big distribution and lots of samples, like the kind you get when you simulate hundreds of thousands or even millions of bits of traffic.

Figure 1. Traditional circuit simulation using a rectangular mask for compliance checking

That feat still wasn’t practical with traditional circuit simulation, which historically gave reasonable run times in the range of hundreds of bits of traffic (see Figure 1). To address this, the first commercial “channel simulation” was introduced. Here, assume linear time invariance (LTI), find the impulse response for the channel, and convolve it with a big input stimulus to generate tons of waveforms very quickly at the receiver. Suddenly a few million bits could be simulated in a couple of minutes, the eye distribution could be distributed, and it could be post-processed to produce bathtub curves and BER could be calculated for the interface (see Figure 2).

Figure 2. Eye densities are post processed to produce bathtub curves for BER analysis

With that in place, the next step was to model the advanced equalization (EQ) that was starting to become common (see Figure 3), like feed-forward equalization (FFE), continuous time linear equalization (CTLE), and decision feedback equalization (DFE). Again, circuit models were way too slow to efficiently model the real-time adaptive EQ, and so AMI was born to provide executable models with an industry-standard (IBIS) API, which could be linked into the channel simulator at runtime. The industry followed suit quickly, and everyone has been simulating serial link interfaces ever since.

Figure 3. Advanced receiver models may employ multiple EQ functions cascaded together

Now it is happening again, but this time with DDR interfaces. With the release of the JEDEC spec for DDR4, DDR memory interfaces shifted from traditional setup and hold timing to mask-based compliance criteria at a particular BER—just like serial links. Then DDR4 controller IP started to use EQ like FFE and CTLE—just like serial links. With DDR5, the memory devices started to use DFE when they received signals—just like serial links (see Figure 4). As the data rates rose, the memory interface topologies started to get closer and closer to point-to-point topologies—just like serial links. Is there a pattern here?

Figure 4. Channel simulation results (2D and 3D) with and without equalization

As memory interface data rates have risen to the heights once occupied by serial links, serial link modeling and simulation techniques have trickled down to DDR territory. For example, in mid-2017, Cadence released the industry’s first AMI model for a DDR device, providing an AMI model for its DDR4 controller IP. Six months later, Micron delivered the industry’s first AMI model for a DDR memory device for its DDR5 DRAM. Using the AMI model for the controller and a Micron AMI model for the memory, a joint customer became the first systems company to run channel simulations for a DDR interface with AMI models.

One of the big differences this time is the ability to generate AMI models. They are like “fuel for the car,” so to speak, with the car being the channel simulators like SystemSI. Back with the first wave of AMI modeling for serial links, one needed to be part programmer, part SerDes architect, and part SI engineer to develop AMI models, largely from scratch. That Venn diagram got very thin very fast, so the few people that existed in the middle of that diagram charged some very big numbers to develop models for those that needed them. With this second wave, tools now exist that make it straightforward to build quality AMI models from a rich set of known good library modules, with a wizard-based UI that walks through the process.

Take, for example, CTLE. These are basically peaking filters, and can be easily described in time domain, real imaginary plots, magnitude vs. frequency, pole zero, or rational function format. These can all be imported into a tool, such as (my company’s) Cadence AMI Builder, as shown below:

Figure 5. Wizard-driven approach to AMI modeling using external files to describe filter characteristics

If you can use SI tools and know something about the EQ you are modeling, you can get there rather quickly now.

Of course, there are other differences, such as single-ended instead of differential signals, and external strobe signals instead of clock recovery. But what was old is new again. Channel simulation and AMI modeling 2.0 is upon us. We can make our own fuel this time and skip the long lines and inflated prices.

I consider that progress.


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