Signal Integrity

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Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.

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Keysight HQ

Keysight Santa Rosa Headquarters Resumes Operations

Keysight Technologies' corporate headquarters in Santa Rosa, California has resumed operations after being temporarily closed due to the wildfires in Northern California. All four main buildings at the site are intact, and the majority of production facilities are back in operation, according to the company. Keysight affirmed the fourth quarter 2017 financial guidance provided in its third quarter earnings release on August 30, 2017.

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Debugging High-Speed SERDES Issues in Multi-board Interconnect Systems

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    

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How to Make Predictable PCB Interconnects Thumb

Lessons learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

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