Gene Saghi is a principal engineer with Broadcom Ltd. He earned a PhD from Purdue University, a MEng degree from Cornell University, and a BS degree from Wichita State University; all in electrical engineering. He has over 30 years of engineering experience ranging from board-level design to ASIC design to teaching and research in electrical engineering at the university level. Currently, he is a hardware architect working on IO controllers and RAID-on-Chip controllers. He represents Broadcom Ltd on the PCI Express Protocol Working Group committee.
PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.