Signal Integrity

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IQD has launched a new range of LVPECL (IQXO-623/IQXO-624) & LVDS (IQXO-618) output clock oscillators with the phase jitter of less than 1ps rms (over 12kHz to 20MHz) irrespective of which output is specified.

Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM4 SerDes and emerging 112G serial applications. With this portfolio expansion, Silicon Labs offers a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.

Rohde & Schwarz introduced the new high-performance R&S RTP oscilloscope. During the development of the new oscilloscope family, the focus was on measurement accuracy, speed, a wide range of functions and future-proof technology.

Keysight Technologies, Inc. today announced that the company will demonstrate AresONE-400G at Interop Toyko (booth 4Y16) to be held June 13-15 at Makuhari Messe in Chiba, Japan. AresONE-400G is the first high-density 8-port 400 gigbit Ethernet (GE) test system in a 2 rack-unit (RU) fixed chassis based on 56Gb/s electrical interface with PAM-4 encoded signaling.

Keysight Technologies, Inc. announced today a new measurement platform that ensures consistent, repeatable results across all phases of design. The new Keysight Streamline Series is comprised of compact USB instruments: vector network analyzers (VNAs), oscilloscopes and an arbitrary waveform generator (AWG) that leverage trusted Keysight technologies, measurement algorithms, and application software.

At this week’s 2018 IEEE International Interconnect Technology Conference (IITC 2018), imec, will present 11 papers on advanced interconnects, ranging from extending Cu and Co damascene metallization, all the way to evaluating new alternatives such as Ru and graphene.

With the MAX22505 ±40V high-speed USB fault protector from Maxim Integrated Products, Inc., designers can now eliminate USB port damage from all faults, including ground potential differences, up to ±40V without the tradeoffs required by competing solutions. It protects data and power lines from industrial equipment powered at 24V_AC and 40V_DC, while also reducing solution size by more than 50% for industrial voltage applications.

Eric Bogatin explains the figures of merit in the time and frequency domain, and he steps through how to get a rough measure of the highest frequency components in a signal.

Eric Bogatin will lead this special session again at EDI CON USA, taking on the topic of how to deliver more than 100A with less than 10 mV of noise to digital devices. See how you can get involved.

Yuiry Shelpnev argues that simulating a link in isolation from the rest of the board (localization) is probably the most important requirement to simulate interconnects predictably. Read on to understand this important concept.