Lane A. Smith is a Director of Engineering at Broadcom Ltd, responsible for storage SerDes design and SAS/SATA Protocol design. He has over 25 years of engineering experience ranging from design to management of several generations of modem and Fibre Channel, SAS, SATA, PCIE SerDes designs. He has over 100 US patents granted in his name in the area of modem, audio codec and SerDes design.
PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.