Signal Integrity

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Due to the ever increasing speed-grade of memory systems, it is necessary to apply equalizations, which creates severe burdens for memory system design engineers. Fortunately, the challenges have been overcome by an IBIS-AMI solution for single-ended signals and the introduction of a forwarded clocking solution. Read on to learn more.

With the growth of 5G data traffic and AI computing, data centers need faster connectivity to meet the increasing bandwidth. High speed I/O speed beyond 112 Gb/s per lane is required. If we follow the SerDes technology revolution by doubling the data rate per lane in every 2-3 years, the next generation I/O data rate will be 224 Gb/s. In this article, Cathy Liu explores options, technical challenges, and potential solutions to achieve 224 Gb/s per lane.

Keysight Technologies, Inc., announced that the company's M8040A 64 Gbaud High-performance bit error ratio tester (BERT) was approved by the PCI-SIG as a compliance test measuring instrument for PCI Express 4.0 (PCIe Gen4) testing at 16 gigatransfers per second (GT/s) and 8GT/s.

While many already had home lab setups for projects and exploring curiosities, the challenges of the global pandemic have driven many to ramp up their set ups and spend more time at their in-house benches. Over the years, Signal Integrity Journal has worked with many leading industry experts and stars in our field. Some have gamely agreed to play along with me and share images of their home labs. Enjoy the tour!

If you are missing your engineering tools, or would like to build up your home lab, or want to finally work on that hobby electronics project you’ve put off for the last five years, or you want to introduce your kids to the thrill of measuring or simulating, now would be a good time to consider our list of free or very low-cost hardware and software simulation tools.

Measuring low impedance components with a 2-port vector network analyzer (VNA) is an essential technique that typically requires a VNA that costs more than $20,000. In this article, see how the authors measured an MLCC using $500 and an open-source simulation tool.

Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance from a uniformly designed transmission line in the SI world, read on to learn more.

The most notable difference between DDR5 and previous generations is the introduction of decision feedback equalization, a technique used in serial link systems to improve the integrity of received signals.  In the wake of the new technology, this short article outlines some of the fundamental signal integrity concepts in the context of DDR5.

We want to follow this mantra of 85 ohms for PCIe, but it may not be so easy. Here’s a look at exactly what the spec says, and what we can do about it.

Gustavo Blando, a Samtec signal integrity architect, recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.