Technical Articles

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This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps.

This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.

Since an oscilloscope and phase noise analyzer observe jitter differently, obtaining the same value from both instruments can be challenging. This article presents a phase-noise based methodology that provides similar values as time-interval error jitter derived from an oscilloscope.

It is important in high-speed digital applications to decrease the form factor and increase signal density by reducing isolating metal layers, all while preserving comparable crosstalk, loss and dispersion at the frequency of interest. This paper takes a look at how you can do that by showing how coplanar waveguide with smaller form-factor outperforms stripline in isolation and coupling.

When you make a 2-port shunt through measurement using a commercial vector network analyzer the measurement includes an undesirable ground loop. Left uncorrected, the ground loop introduces significant errors. This paper shows how to solve this problem.

Wondering about the practical uses of the proposed IEEE P370 standard? This  paper shows some applications of the draft IEEE P370 standard in order to demonstrate its effectiveness for interconnect measurement.

The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.

That’s the question that will trigger your amygdala’s fight or flight response as you encounter the many annoyances that PAM4 brings to your world. Since you’re in a lab rather than a jungle, that fight or flight response might translate into sarcastic cracks like: “Right, that higher BER requirement makes it all so much easier—not.” “Good old NRZ, those were some fine bits. Remind me why I asked for this?” And, “dear NRZ, I never knew how much I loved you until I lost you.”

A particularly challenging configuration is the edge launch, where connectors are used on the edge of the PCB with a transition to a microstrip trace. A poorly optimized connector footprint leads to degradation of the signal integrity performance, especially at high data rates. This paper identifies the root cause of the problem by showing how the electromagnetic fields behave at the transition area. Then it presents a design methodology, using simulated and measured data, that ensures the quality of high-speed data transmission.

Switch-mode power supplies (SMPS) are commonly used DC-to-DC converters in many electronic components. By their nature, they can generate a lot of radiated emissions. Unless care is taken, it is difficult to separate what is the actual voltage on the power rail and what is an artifact due to the way we probe the circuit. The project outlined here shows how to avoid EMI pick-up and cable reflection noise.