Heidi Barnes

Heidi Barnes is a member of the Design Engineering Software Group at Keysight Technologies. Her recent activities include the application of electromagnetic, transient, and channel simulators to solve signal and power integrity challenges. She has authored over 20 papers on SI and PI, is an active member in developing the new IEEE P370 standard involving interconnect S-parameter quality after fixture removal, and received the DesignCon 2017 Engineer of the Year award. Heidi holds a BS EE degree from Caltech.

Optimizing Power Distribution Networks for Flat Impedance

May 12, 2020

Heidi Barnes

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It takes only one rogue voltage wave to kill a PDN in high-speed digital designs. Flat impedance optimization before layout lowers the risk of rogue waves occurring in your design. Heidi Barnes explains how rogue waves occur and addresses how to get the best performance at the lowest cost.

Practical Application of the IEEE P370 Standard for Measurement of Interconnects up to 50 GHz

March 25, 2019

Jay Diepenbrock, Heidi Barnes, Eric Bogatin, Ching-Chao Huang, Jason Ellison, Mikheil Tsiklauri Ph.D., and Xiaoning Ye Ph.D.

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Wondering about the practical uses of the proposed IEEE P370 standard? This paper shows some applications of the draft IEEE P370 standard in order to demonstrate its effectiveness for interconnect measurement.

IEEE P370: A Fixture Design and Data Quality Metric Standard for Interconnects up to 50 GHz

March 12, 2019

Jay Diepenbrock, Eric Bogatin, Heidi Barnes, Jason Ellison, Mikheil Tsiklauri Ph.D., Xiaoning Ye Ph.D., and Ching-Chao Huang

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The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.

Accurate Statistical-Based DDR4 Margin Estimation Using SSN Induced Jitter Model

March 1, 2017

HeeSoo LEE, Cindy Cui, Heidi Barnes, and Luis Boluna,

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Here's a proposed method that improves the accuracy of DDR4 statistical simulation by using the mask correction factor. It presents a validated correlation between measured and simulated data to show that this methodology can be effectively used for DDR4 design

Signal Integrity Tips and Techniques Using TDR, VNA and Modeling

March 14, 2016

Heidi Barnes, Jeff Most, and Mike Resso

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Heidi Barnes

ARTICLES

Optimizing Power Distribution Networks for Flat Impedance

Practical Application of the IEEE P370 Standard for Measurement of Interconnects up to 50 GHz

IEEE P370: A Fixture Design and Data Quality Metric Standard for Interconnects up to 50 GHz

Accurate Statistical-Based DDR4 Margin Estimation Using SSN Induced Jitter Model

Signal Integrity Tips and Techniques Using TDR, VNA and Modeling

SIGNAL INTEGRITY JOURNAL