Technical Articles

AI-Assisted HFSS Modeling For 100 GHz+ High-Speed Interconnect Design

Thu, 23 Apr 2026 00:00:00 -0400

Why Power Architectures Constrain New Space AI Missions

Wed, 22 Apr 2026 00:00:00 -0400

Ultra-Low Insertion Inductance, Ultra-High-Bandwidth Resistors

Tue, 21 Apr 2026 00:00:00 -0400

By treating the resistor as an electromagnetic structure rather than a lumped element, and by managing coupling, shielding, thermal paths, and compensation as part of a unified design, it becomes possible to achieve ultra‑low insertion inductance and gigahertz‑class measurement bandwidth in a device small enough for production use. The result is a measurement element that enhances system performance rather than limiting it. As power systems continue to push toward higher speed, higher density, and higher reliability, the current‑sense resistor must evolve accordingly. In this article, Steve Sandler outlines a path to that evolution.

SIJ Publishes April 2026 Issue

Sat, 18 Apr 2026 00:00:59 -0400

Signal Integrity Journal, covering signal integrity, power integrity and EMC/EMI, has published its April 2026 issue. Don't miss out on the latest. Download now!

The Role of Copper Pour and Picket Fence vias in Digital Designs

Fri, 17 Apr 2026 00:00:00 -0400

Sensitivity of PCIe Connector Return Loss to Mating Interface and PCB Footprint Impedance Variations

Thu, 16 Apr 2026 00:00:47 -0400

Machine Learning Models for SI/PI Analysis with Meshed Planes

Wed, 15 Apr 2026 00:00:00 -0400

OneWeb Satellite’s 50V/10 Half-Bridge Driver Development

Thu, 19 Mar 2026 00:00:00 -0400

By leveraging radiation-hardened GaN HEMTs and a compact, high-efficiency design, EPC Space not only met the stringent demands of size, weight, reliability, and performance, but exceeded them, delivering modules that have proven their worth in the harsh environment of space. Read on to learn more about how this success underscores the potential of GaN-based solutions to drive the next generation of satellite systems, paving the way for more affordable, sustainable, and resilient space exploration.

Mitigating Ground Loop Errors in High-Current PDN Measurements: Validating Measurement Accuracy Across Oscilloscope Platforms

Mon, 16 Mar 2026 01:00:00 -0400

As currents increase and voltage rails shrink, managing fluctuations becomes a critical challenge. While probe noise is a major factor, the common-mode noise induced by the ground loop between the high-current DUT and the oscilloscope is often the more dominant disruptor in high-current AI environments. This experiment proves that simply switching oscilloscope vendors will not solve the problem. Read on to learn why the solution lies in the probing chain.

Optimization of IBIS-AMI Model Parameters with Machine Learning Algorithms

Wed, 18 Feb 2026 00:00:00 -0500

This article describes the use of Cadence’s Sigritysignal and power integrity solution ML optimization algorithm to quickly and efficiently converge on the best set of parameters in a set of IBIS-AMI models. The application of Sigrity was investigated for refining IBIS- AMI parameters to find the optimal set of values to maximize a specific metric.

How to Simulate Uniform Transmission Lines at Low Frequencies

Wed, 11 Feb 2026 00:00:00 -0500

This article details the electromagnetic simulation of low frequencies in Ansys Electronics Desktop, focusing specifically on arbitrary length transmission lines and cables with uniform cross sections. It presents two-dimensional, quasi-static field and circuit solvers as an alternative simulation method, covering the simulation workflow while highlighting the differences and benefits of using this method as opposed to using predominant full-wave field solvers.

Material-Induced Skew in High-Speed Multilayer PCBs: Influences and Mitigation Strategies

Sat, 17 Jan 2026 00:00:00 -0500

Among various forms of signal degradation, skew is a key contributor to timing errors in systems operating at multi-gigabit data rates. An increasingly important factor at high speeds is material-induced skew due to local differences in dielectric constant arising from the PCB’s woven glass fabric reinforcement. This article aims to unpack the root causes of material-induced skew, particularly focusing on the glass weave effect, and explores mitigation techniques ranging from laminate selection to signal routing strategies.

The Imperfect Via: The Rough Truth Lurks Beneath the Surface

lsimonovich@lamsimenterprises.com — Sat, 10 Jan 2026 00:00:00 -0500

Bert Simonovich explains why material anisotropy is not solely responsible for contributing to Dkeff surrounding a via hole structure. The via barrel conductor roughness and resin content of the as-fabricated dielectric pressed thicknesses must be considered and adjusted before applying this heuristic method to calculate Dkxy.

Evolution of PCIe Beyond Gen7: PCIe Gen8

Sat, 13 Dec 2025 00:00:00 -0500

The PCIe standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. Follow along as Abhijit Wander explores how sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

Using Ultra-Broadband Baluns to Perform Differential S-Parameter Measurements Using Single-Ended 2-Port VNA

Tue, 09 Dec 2025 00:00:00 -0500

This article demonstrates accurate differential S-parameter measurements obtained from a single-ended 2-port VNA using ultra-broadband baluns and attenuators. This measurement system is a cost-effective alternative to purchasing a multi-port test set for a VNA.

High-Speed Digital Interface Characterization Requires New Test Approach

hiroshi.goto@anritsu.com — Thu, 20 Nov 2025 00:00:00 -0500

The increasing speeds of digital interfaces to meet the ever-growing data demands of modern society places stress on design engineers. A new test methodology for measuring intra-pair skew is necessary to verify high-speed interfaces such as PCI Express. The BERT-based setup uses a new method with dual transmitters to control the phase of signals within a differential pair, enabling granular measurement of intra-pair skew. This capability is crucial for understanding and mitigating the impact of skew on BER margins at high data rates such as 64 GT/s.

Seeing Through the Noise: Reliable Power Rail Measurements in High-Current AI Systems

Wed, 19 Nov 2025 00:00:00 -0500

In this article, power rail voltage measurement uncertainty is examined using several different probe configurations to monitor VCore measurements on a Picotest S2000 load stepper board. The results reveal measurement variations up to 27 mV — a level of uncertainty that can completely mask the performance improvements engineers are seeking from advanced VRM technologies. Read on to learn how engineers can trust their measurements when the uncertainty exceeds the performance gains they are trying to validate.

Electrical and Thermal Simulations of Electronics in the AI Age

Thu, 30 Oct 2025 00:00:00 -0400

This article discusses electrical and thermal co-simulation of multi-pin interconnects. Using Ansys Q3D and Icepak (2025R1), it highlights key practices such as parametrization, matrix reduction, and mesh settings to ensure accurate and efficient results with complex geometries.

You Measured What? Four Must-Know Checks Before Trusting Your Trace S-Parameters

Mon, 27 Oct 2025 00:00:00 -0400

S-parameter data can reveal more than what it initially shows. This article presents four key insights that can be derived from your S-parameters, enabling smarter simulation and improving your signal integrity intuition.

Superconducting Interconnect: The Effect of Kinetic Inductance on Signal Integrity

haider.clifton@mayo.edu — Wed, 22 Oct 2025 00:00:00 -0400

While the lossless characteristics of superconducting interconnect can trigger visions of tremendous bandwidths over infinite physical distances, superconductors have unique properties that can appreciably affect signal integrity in unexpected ways. This article introduces kinetic inductance from the eyes of signal integrity with the aim of preparing engineers to analyze superconducting links.

ManyPoint Networks: A System Co-Design Framework for 448 Gbps AI Fabrics and Beyond

Sun, 19 Oct 2025 00:00:00 -0400

This article introduces a hardware-centric definition of compute cluster bisection bandwidth as a performance metric for AI-scale 448 Gbps systems. Unlike traditional abstractions, this metric is grounded in physical interconnect layout and IO port availability, enabling system architects to evaluate bandwidth provisioning through real, bidirectional link paths.

EMC Challenges in EV Systems

Sat, 27 Sep 2025 00:00:00 -0400

In a high-power system, such as the high-voltage side of electric vehicles (EVs), even small imperfections in the topology and layout inside the box can have major consequences in EMC testing. Parasitic pathways that would be inconsequential in a low-voltage design can allow limit-busting amounts of noise to escape in a high-voltage system. Learn more from Karen Burnham about the best practices, simulation/analysis, and expert design reviews that are critical for EV compliance and on-time deliveries.

Cable Resonance in Automotive Component EMC Tests

Tue, 23 Sep 2025 00:00:00 -0400

This article covers some typical failure cases for automotive EMC tests in which the cable resonances play dominant roles. It explores the mechanisms of cable resonance, providing test examples and simulation results to demonstrate root causes. Learn more about system design details that impact cable resonance behavior.

Causality in Practice: How Frequency Sampling and Bandwidth Shape Time-Domain Fidelity

Sun, 14 Sep 2025 12:00:00 -0400

In this article, Tyler Huddleston explores causality in relation to signal and power integrity simulations. He reviews how causality affects time-domain simulation fidelity as well as how non-causal s-parameters can result from real measurements and simulations. Learn about how non-causal data can be avoided and the consequences of using a non-causal model in time-domain simulations.

Path to 400G May Require Alternative Architectures

Mon, 01 Sep 2025 00:00:00 -0400

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.

AI Data Centers Move Capacitors Back into the Spotlight

Sat, 16 Aug 2025 00:00:07 -0400

AI data centers are power hungry, pushing power density to new highs while requiring long-term reliability. The increasing power density, particularly at the board and rack levels, creates challenges for stability and the unpredictable high-current surges resulting from these many-core applications. These difficulties are driving a significant amount of new development in capacitors while also inspiring the repurposing of older technologies. Sandler examines the opportunities and challenges presented by evolving demands in the power integrity sector.

Innovative Layout Optimization Methodology and Via Routing Pattern to Enable UCIe-36 Gbps in Organic Interposer

Sat, 09 Aug 2025 00:00:00 -0400

This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.

Innovative Interposer Solutions for HBM3/4: A Path to 12.8 Gbps

Thu, 07 Aug 2025 00:00:00 -0400

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.

Futuring Interconnect Infrastructure for AI: RF Transmission over Plastic Cable Surpasses Copper and Optics at Terabit Scale

Mon, 04 Aug 2025 00:00:00 -0400

Point2 Technology’s e-Tube offers a compelling alternative to copper cables and optics. It extends copper’s reliability and economics to support terabit-scale data rates in a lightweight, power-efficient, and highly manufacturable form to address short reach, AI cluster scale-up in data centers. With roadmap scalability to multi-terabit and compatibility with standard cable form factors, e-Tube redefines the compute fabric for next-generation AI clusters.

Roll Your Own TDR

Mon, 28 Jul 2025 00:00:00 -0400

This article presents a simple yet effective method to roll your own TDR using any square wave source, any scope, and an affordable power splitter. This low-cost approach offers a practical and accessible solution for characterizing transmission lines in educational or resource-constrained lab environments.