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This paper focuses on the importance of DCD jitter analysis at higher speed and heavier loading NAND systems, and introduces a statistical approach to DCD jitter analysis.

Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. This article provides a brief description of the SPI interface followed by an introduction to Analog Devices’ SPI enabled switches and muxes, and how they help reduce the number of digital GPIOs in system board design.

New power-semiconductor technologies like SiC and GaN enable increased efficiency and higher switching frequencies, which allows smaller component sizes. But these gains come at the expense of greater radiated electromagnetic emissions, just as EMC regulations are getting tougher. How can engineers effectively minimize radiated EMI?

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.

Receiver sensitivity and noise coupling to antenna are two major concerns when developing mobile devices such as smart phones and tablets. There are various causes of degradation of receiver sensitivity. However, most of the time they are due to the noise generated by digital signal harmonics on printed circuit board (PCB) patterns, which couple to the antennas. This article presents a methodology to predict noise to antenna coupling and antenna desense.

Power conversion circuits with control loop(s) are everywhere in electronic systems. We must establish stability and performance metrics for control loops and their circuits. However, generally accepted metrics may not be good enough. Is a crossover frequency with 45 degrees of phase margin and 10 dB of gain margin enough? How can we relate phase margin to peaking in the impedance profile and transient noise requirements? This article aims to answer these and other questions.

VRMs and VRM controllers are often selected based on size, efficiency, price, or a relationship with the manufacturer. This often leads to a poor VRM selection, requiring additional engineering resources, greater time to market, as well as, higher BOM costs to correct the deficiencies. In this article, we evaluate the choices, define some useful figures of merit, and provide specific selection suggestions.

This article examines the key noise processes involved in measurements of jitter and phase noise, shows how these processes impact test results for various types of test equipment, and provides insight for interpreting these results.