Raul Stavoli

Raul Stavoli is a Signal Integrity Engineer at Carlisle Interconnect Technologies, who specializes in high frequency design. He received a bachelor’s degree in electrical engineering from San Francisco State University in 2014. Upon graduation, he worked as a Signal Integrity Engineer in the Copper Solutions group at Molex, LLC. He designed 1Gb and 10Gb Ethernet magnetic jacks, PCBs, magnetics, performed simulations for the design of I/O and backplane products(40Gb/s) and developed MATLAB based software for time and frequency domain analysis. In addition, he assisted the NBase-T committee in the development of the 2.5Gb and 5Gb ethernet standard and products. He is currently working on RF and high speed digital connector design as a member of the Carlisle SI team. When he is not in the office, his personal interests are trail running, playing soccer, studying history and physics.


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Demystifying Edge Launch Connectors

A particularly challenging configuration is the edge launch, where connectors are used on the edge of the PCB with a transition to a microstrip trace. A poorly optimized connector footprint leads to degradation of the signal integrity performance, especially at high data rates. This paper identifies the root cause of the problem by showing how the electromagnetic fields behave at the transition area. Then it presents a design methodology, using simulated and measured data, that ensures the quality of high-speed data transmission.

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