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Power distribution networks (PDNs) delivering power to ICs in a system need to be thoroughly designed and analyzed in order to make sure any voltage fluctuation on the rail is within the tolerance of every IC connected to that rail.  As ICs on the rail draw power, they generate a voltage fluctuation on the rail.  The PDN must have the capacity to supply enough charge such that the resulting voltage drop is less than the maximum voltage drop each IC on the rail can tolerate.  If voltage fluctuations appear outside IC tolerance limits, a slew of problems can surface such as IC damage, failure, or reduced lifespan.

The current trend for many application requiring data converters is to get closer and closer to a full SDR (Software Defined Radio) system. While SDR architecture brings many benefits in terms of flexibility and SWaP-C (Size, Weight, Power and Cost) it often translates into higher bandwidth capability and is directly linked to the data converter sampling speed with the Shannon-Nyquist theorem.

At DesignCon 2018, the IEEE P370 standards group announced the release of two important tools to assist all engineers for de-embedding. In the presentation by Jason Ellison and Heidi Barnes, “A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics”, the two new tools were announced, a board kit and a de-embedding software tool.

DesignCon has been a tremendous source of information for myself and for the team I have been working with at SUN Microsystems, which later became part of Oracle Corporation. This summary is an attempt to capture some of the most influential papers from the past twenty years that made the biggest impact on our work.

This article presents a method for power integrity analysis in FPGA systems by configuring the FPGA to function as a vector network analyzer (VNA) test instrument for its own power distribution network (PDN).

It’s what you don’t know you don’t know that can ruin your day. This paper notes in detailed examples that with today’s high-speed designs, we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three disciplines and become educated about each of them to achieve successful designs.

A negative coupling coefficient between decoupling capacitors is expected to result in lower inductance.  While this is generally the case, this can also result in much higher PDN impedance.

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.