Jonggab Kil joined Intel in Folsom as an engineer in 2006. Since then, he built up a broad experience with circuit design, power delivery and signal integrity. He published multiple patents regarding signal integrity and high-speed I/O design enhancement. He also published papers to JSSPI and DTTC as a presenter regarding a new method of on-die and platform power/signal integrity analysis. His current research interests include power/signal integrity design automation and efficiency improvement.
In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.