Vijay Kasturi is currently Sr. SI/PI Engineer at Intel, Folsom, working on I/O modeling and SI/PI solutions for next-gen IP Products. He has 14 years’ experience in the SI/PI areas and co-authored multiple IEEE and Intel internal papers and patents.
In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.