Signal Integrity

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Each of the five experts presented a different approach to incorporating material properties in simulations to accurately predict a channel’s performance. Read on to see what they had to say.

Wondering what IBIS Open Forum actually does? Mike LaBonte lifts the curtain and invites you to learn more about IBIS models.

JitterLabs announces the immediate availability of an independent test program for evaluating reference clock compliance to PCI Express® (PCIe®) v4.0 BASE specifications, covering all four generations of PCIe technologies (2.5 to 16 GT/s).

If you want help measuring things, there’s no cheaper way to do it than this!

Read on to see how to determine if you should you use a differential pair in your test coupon and pay for a 4-port measurement, or use a single-ended test line and only pay for a 2-port measurement.

In this DDR 101 introductory piece, learn about the fundamentals of a DDR interface and some basics of physical-layer testing.

Component simulations cannot be properly compared to measurements without de-embedding the test fixture—here’s step-by-step instructions to get the job done well.