Richard Allred has over a decade of signal integrity design experience at Intel, Inphi, SiSoft, and MathWorks. He holds one signal integrity related patent, has authored dozens of IBIS-AMI models and is currently developing signal integrity tools at MathWorks. Richard received his MS/BS in 2006 from the University of Utah.
In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.
This paper will demonstrate the application of DOE and RSM to a CEI 28G VSR design. We will show the process of creating a DOE, fitting the data to models, determining the goodness and reliability of the fit and then using the model to perform “what if” analysis, optimize design factors and quantify the impact of manufacturing variation.