Figure 1 Various timing applications.
As requirements for stable, low-jitter clocks grow in hyperscale data centers, so does the complexity of the ubiquitous timing devices. Timing is a foundational requirement for hyperscale data centers and next-generation AI factories. As hyperscalers deploy increasingly powerful GPU clusters to train and serve AI models, stable and low-jitter timing supports high speed interfaces, synchronization mechanisms and reliable data movement across the system (see Figure 1).
AI infrastructure is no longer a collection of loosely connected servers. It is evolving into rack-scale computing platforms that behave as unified silicon systems. In this architecture, stable, low-jitter timing is what allows thousands of processors to operate as a coherent whole.
The performance of GPUs continues to scale dramatically, processing thousands of billions of operations per second. To support this, hyperscalers require timing solutions that deliver stability, low phase noise, minimal jitter and synchronization across boards, trays and racks. As bandwidth increases and latency budgets shrink, timing is becoming one of the most critical enablers of AI deployment at scale.
HIGH SPEED INTERFACES AND SIGNAL INTEGRITY
As AI infrastructure continues to scale, maintaining reliable high speed electrical and optical interfaces has become an increasingly important aspect of overall system design. While compute architecture and software frameworks remain the primary drivers of performance, signal integrity at multi-hundred-gigabit data rates plays a meaningful role in determining how efficiently that performance can be delivered. As bandwidth increases and port densities rise, timing stability becomes one of the factors that support consistent and predictable operation.
Modern switch ASICs deployed in AI networking platforms now integrate hundreds of high speed SerDes lanes operating at 112 Gbps and 224 Gbps per lane. At these data rates, each bit occupies only a few picoseconds, leaving limited timing margin within the link budget. The reference clock does not solely determine link performance, but its phase noise characteristics contribute to total system jitter, which influences eye opening, jitter tolerance and overall link robustness.
Within each SerDes lane, phase-locked loops (PLLs) multiply and condition the reference frequency to generate the required high speed clocks. The oscillator’s phase noise is shaped by these PLLs and becomes part of the overall transmit and receive jitter profile. If the accumulated jitter approaches system limits, signal margin narrows and the link may rely more heavily on equalization and forward error correction. In some cases, this can increase power consumption or introduce retransmission overhead, reducing overall efficiency.
In pluggable optical modules, clock data recovery (CDR) circuits extract timing from incoming data transitions. The quality of the host reference clock contributes to the jitter environment experienced by both transmitter and receiver, particularly in dense switch designs where multiple high speed lanes operate in close proximity. Stable frequency control and low phase jitter help maintain cleaner signal transitions and consistent link behavior.
Figure 2 Phase noise and jitter at 312.5 MHz. Also shown are the 2520 and 2016 package oscillators.
Across switches, pluggable modules and SerDes subsystems, lower phase jitter and stable frequency references help preserve transmitter eye margin, support robust CDR operation at the receiver and contribute to more consistent latency behavior in high speed links. As AI networking platforms continue to scale in bandwidth and integration density, careful management of timing and jitter budgets remains an important component of reliable optical and electrical interconnect design.
As AI networking transitions toward higher lane speeds and greater optical density, precision timing becomes a critical enabler of signal integrity and scalable performance throughout the data path. The latest generation of crystal boosts the fundamental frequency from 500 to 700 MHz, with stable operation at higher temperatures, helping module and switch designers tackle these thermal and performance challenges.
Increasing the fundamental frequency means reduced noise introduced by the multiplier. The latest crystal oscillator uses the same form factors of 2.5 × 2 mm and 2.0 × 1.6 mm to fit into the same space in a module or on a board, while boosting performance with lower phase jitter and noise, and operating at higher temperatures (see Figure 2). Operating up to 105°C and down to -40°C without derating gives designers more headroom to implement the clock tree for rack-sized processing units.
This performance comes from optimizing the size, shape and etching of the crystal to optimize the resonant frequency and the tightness of the resonance, the Q factor, for stable oscillation with lower noise.
The resonant frequency of the crystal depends on the cut and thickness. Creating a 700 MHz resonant frequency with the required connections requires significantly more shape-engineering proficiency than 500 MHz, ensuring durability and a stable frequency.
Figure 3 Turning synthetic quartz into crystal units. Autoclaves are used to grow seed crystals into synthetic quartz blocks.
Figure 4 Crystal blanks are shaped into finished products, from tuning fork crystals to high frequency oscillators.
The stable tolerance across the entire temperature range is a key improvement. One important factor is behavior at higher temperatures. End-to-end in-house production also allows the production of the crystal to be optimized for the design. Growing the crystal in-house rather than using naturally occurring crystals allows for control over crystal quality, with tight control of impurities (see Figures 3 and 4). This also provides supply chain reliability. With the explosive growth in AI investment, ensuring the supply of components and boards is critical. Having control of the production of the crystals allows the manufacturer to ramp up to meet demand rather than relying on third-party suppliers.
For the third-generation high frequency fundamental crystal oscillator available later this year, an updated driver and IC provide flexibility in the oscillator’s output swing, all in the same small footprint as the previous devices. This allows the module designers flexibility to choose a custom swing that is tailored to their design. This is aimed at board and optical module designers who want the voltage swing at a very specific level, depending on the controller ASIC.
Noise will always be a key issue in the optical module due to the proximity of all the components, so providing a lower noise floor across a wider temperature range will improve the performance and reliability of next-generation high performance optical modules. The IC reduces the noise from the crystal and filters out the noise from the power rail with a combination of filters and digital signal processing algorithm via a low dropout regulator.
AUTOMOTIVE
The same GPU technology that is being rolled out in the AI factory is also making inroads into vehicles for a range of applications. The latest embedded processors for Advanced Driver Assistance Systems rely on oscillators for radar, lidar and camera processing. These components require low-jitter performance to ensure split-second decision-making in autonomous braking or lane-keep assist. Vehicle-to-everything (V2X) communication and 5G integration also demand high frequency stability to maintain data integrity while the vehicle is in motion. The move to software-defined vehicles brings many of these features together into a central high performance processor with higher frequency requirements than previous devices.
The components must be qualified to AEC-Q200 standards, meaning they are tested to withstand extreme temperatures and operate reliably from -40°C to +125°C. The latest generation of crystal will meet this requirement, but the devices also have to withstand constant engine vibrations and road shocks with mechanical robustness and operate without interference from the heavy electromagnetic noise generated by electric motors in electric vehicles.
CONCLUSION
Optimizing the design of an oscillator to increase stability at higher temperatures is a key requirement for the timing networks of current and next-generation optical networking. Boosting the fundamental frequency to 700 MHz helps simplify the timing network and improve performance in existing and new designs. Reducing phase jitter and noise is a key element of the hardware that supports optical networking and AI scalability.
Stable operation across a wider temperature range in the same small footprint allows server board and optical module makers to reduce jitter and noise, improving performance with minimal hardware changes. The next generation of oscillators with customized output swings, higher frequency operation, and a wider temperature range opens new design options for board and module designers to provide timing networks with greater reliability and a secure supply chain.