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In this article, Bert Simonovich shows how using Dkeff calculated from phase or time delay measurement method will lead to inaccurate simulation results for printed circuit board (PCB) transmission lines.

A high percentage of EMI failures are related to structure resonances in a system. This hands-on article reviews work on structure resonances and their EMI impact, presents methods to identify and locate structure resonances, and suggests fixes using practical examples. 

What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.

Understanding and minimizing discontinuities is increasingly important as serial links become both shorter and faster. Applying the old edge rate to roundtrip relationship to the modern era, Donald Telian in this article offers a rule-of-thumb to help gauge which interconnect structures, and hence discontinuities, to care about – and to what degree.  

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.

DesignCon, the premier high-speed communications and system design conference returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits April 5-7, 2022.

This article is from Chapter 2 of the eBook "The Printed Circuit Designer's Guide to...Thermal Management: A Fabricator's Perspective" authored by Anaya Vardya, CEO, American Standard Circuits, and published on iConnect007 here.

Recent studies indicate that the industry is nearing the precipice where plated through hole via technology has reached a limit in supporting serial links with 28 GHz Nyquist frequency requirements. At DesignCon2021, a team from the Mayo Clinic presented this paper about their work to extend the “life” of conventional PCB technology.

With the recent introduction of the Averatek Semi-Additive Process (A-SAP) process, linewidths under 1 mil are possible using the same fabrication processing line as for traditional 4 mil wide lines. This opens up the possibility of using narrower traces in the BGA escape region than in long-path routing regions. However, using this routing architecture means the narrower traces in the BGA escape field are at a higher impedance than the wider, 50 ohm traces in the routing region. So, how long can these traces be before the impedance mismatch is a problem? The authors of this piece propose an analysis methodology to find out.

If you have designed a controlled impedance transmission line based on a PCB stack-up, how do you know if the PCB fabrication house or another vendor built your stack-up to meet your controlled impedance specification?