Cathy Ye Liu, distinguished Engineer and director, currently heads up Broadcom SerDes architecture and modeling group. Previously she worked as R&D director and distinguished engineer in Avago/LSI which acquired Broadcom in 2016. Since 2002, she has been working on high speed transceiver solutions. Previously she has developed read channel and mobile digital TV receiver solutions. Her technical interests are signal processing, FEC, and modeling in high-speed optical and electrical transceiver solutions. She has published many journal and conference papers and holds 20+ US patents. Cathy has demonstrated her leadership roles in industry standard bodies and forums. Currently she serves as a member of the board director of Optical Internetworking Forum (OIF), a member of the board of advisors for the department of Electrical & Computer Engineering (ECE) of University of California at Davis and the co-chair of the DesignCon technical track of high speed signal processing, equalization and coding. She received her B.S. degree in Electronic Engineering from Tsinghua University, China, in 1995 and received her M.S. and Ph.D. degrees in Electrical Engineering from University of Hawaii in 1997 and 1999, respectively.
With the growth of 5G data traffic and AI computing, data centers need faster connectivity to meet the increasing bandwidth. High speed I/O speed beyond 112 Gb/s per lane is required. If we follow the SerDes technology revolution by doubling the data rate per lane in every 2-3 years, the next generation I/O data rate will be 224 Gb/s. In this article, Cathy Liu explores options, technical challenges, and potential solutions to achieve 224 Gb/s per lane.
Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?
Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.