Technical Articles

DesignCon Paper Summary Samtec 10-18-24.jpg

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization

DesignCon 2024 Best Paper Award Winner

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm



Read More
Samtec DesignCon Paper Summary Cover.jpg

Are 1.0 mm Precision RF Connectors Required for 224 Gbps PAM4 Verification?

DesignCon 2024 Best Paper Award Winner

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 


Read More
Compute Accurate Short Term Frequency Stability  Metrics of Periodic Timing Signals Cover 10-2-24.jpg

Compute Accurate Short Term Frequency Stability Metrics of Periodic Timing Signals

Making accurate time interval error (TIE) or phase noise measurements of a periodic signal presents a number of challenges. The program jitterhist includes algorithms and settings to provide accurate TIE measurement results for periodic waveforms with significant amounts of high-frequency measurement/modulation noise as well as for waveforms having multiple unit intervals of low frequency modulation when the time span of the samples includes more than one period of the modulation. 


Read More
200+ Gbps Ethernet Forward Error Correction (FEC) Analysis Cover 9-3-24.jpg

200+ Gbps Ethernet Forward Error Correction (FEC) Analysis

DesignCon 2024 Best Paper Award Winner

In order to study what is needed and what has been adopted for the next Ethernet speed node of 200 Gbps per lane, this DesignCon 2024 paper, a recipient of the Best Paper Award, investigates different FEC schemes such as end-end, concatenated, and segmented FECs, examining how these different FEC schemes affect signal integrity and performance in different end applications. 


Read More
Who Put That Inductor in My Capacitor Cover 2024.jpg

Who Put That Inductor in My Capacitor?

This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.


Read More