Technical Articles

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In this paper, Will McCaffrey examines the Analog Devices Inc. LTM4650A micro-module with an internal inductor, comparing the generated small-signal passive model from LTpowerCAD to a measured model using the LTM4650A evaluation board. 

This DesignCon paper analyzes the mathematical/theoretical issue in the previous interference tolerance test standards, and discusses two types of reference TX jitter parameters estimation methods to solve or alleviate the issue. Read on. 

This DesignCon paper concentrates on the diverse abilities of AWGs to generate the signals required for compliance to standards such as HDMI 2.1, MIPI C-PHY, MIPI D-PHY, and MIPI A-PHY. Read on. 

This DesignCon 2022 paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases from architectural definition, through analog and digital design, to design validation.

This DesignCon 2022 paper focuses on the use of models for overall system validation, including both system models that evaluate the end-to-end link performance, and models used for individual block functionality to validate a mixed-signal design.

In this paper, John Baprawski gives an overview of modeling SerDes systems in a channel simulator, introduces the zero-cost tools available at SerDesDesign.com, and gives an example of simulating a SerDes system with Tx and Rx IBIS-AMI models – all to bring the SI engineer a low cost path for modeling and simulating SerDes systems.

In this article, Bert Simonovich discusses crosstalk, NEXT vs coupled length in stripline, NEXT vs coupled length in microstrip & FEXT. Read on. 

This paper presents two modeling methodologies for ADC-based SerDes that mitigate IBIS-AMI architectural misalignments, and a corresponding model correlation methodology.

In this article, Douglas Brooks and Johannes Adam illustrate how the thermal impacts of heated traces and pads are not limited to the board layer on which they exist; read on to see how they are reflected on every board layer above and below them.

In this paper, the signal integrity design challenges of 224Gbps-PAM4 networking system are analyzed, and the key enablement solutions are proposed to meet the end-to-end (E2E) loss budget of ≤ 40 dB.