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In Donald Telian’s book he reveals his steps for successful serial links, called the “7 Steps to Successful Serial Links.” In this article, he discusses his most important steps: (one) minimize discontinuities, and (two) manage loss.  

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  

This article shows the impact of using one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method for accurately correlating signal integrity simulations to measurement.

In this power-electronics article, we focus on noise measurement of 48 V range voltage regulators (VRs), up to a maximum of 65 V. We propose a noise measurement setup and examine this method.

In part one of this article, Bert Simonovich explained how air entrapment is the primary reason for Dkeff and phase delay discrepancies between simulation and DUT measurements. Read on to discover how to fix this issue.

Since the inception of IBIS, the IBIS Committee has been working to improve and accommodate limitations of the model. This article gives a synopsis of that history, along with detailing the latest version, IBIS 7.1.  

In this article, John Baprawski reviews various issues when using S-parameter files to represent the channel in a SerDes system channel simulator. Stepping through several detailed examples, he demonstrates how paying close attention to the quality of the S-parameters allows you to have confidence in the derived SerDes design eye diagrams and other analysis methods. 

In this overview of the principles of high-performance PCB layout, Joe Aguilar illustrates thermal design approaches, supplies a synopsis of the power delivery network (PDN), tells strategies for routing high currents with reduced impedance, and provides important considerations for designing effective decoupling capacitance. 

In this article, Donald Telian shares an excerpt from his new book, “Signal Integrity, In Practice,” exploring how optimizing SES both fixes problems and improves system performance. He posits it’s crucial for hardware and SI engineers to understand how to optimize SES; read on to see why he attributes such importance to it. 

Fiber weave effect (FWE) skew, also known as glass weave skew (GWS), is becoming more of an issue as bit rates continue to soar upwards. Today’s 56 GB/s is state of the art in high-speed routers and 112 GB/s is just around the corner. While next-generation PCIe, used in the personal computer and server industry, is rapidly moving to 64 GT/s.