Your serial link is failing its insertion loss (IL) mask, so you remove loss, right? Correct. But it’s also failing its return loss (RL) mask, so you remove discontinuities, right? Maybe, but probably not. IL and RL are, by definition, opposites. IL tells you what gets through an interconnect, while RL tells you what reflects back. So it makes sense that they would have different cures. This article will assert discontinuities don’t sum the way loss does. If you’re failing an RL mask, there’s a good chance your Tx or Rx is simply too close to a discontinuity. This is the discontinuity proximity effect (DPE). You see, unlike IL, for DPE, it’s generally not the sum of discontinuities that causes RL to fail, but rather, how close they are.
Think about it this way. RL measures reflections, or the portion of an injected signal that bounces back. If you throw a basketball, as hard as you can, against a brick wall that is one foot away, when it bounces off it will have more force than if the wall was 10 feet away, right? Perhaps, as it traveled to the 10 foot wall, the ball encountered loss? Could it be that propagation loss makes serial links behave the same way? Let’s explore this idea with some examples.
To illustrate my point that RL measures discontinuity proximity, consider the red line in Figure 1. Here I’ve simulated a 4 in. interconnect in which I have inserted a single 50 mil discontinuity at different distances from the point where RL is measured (X axis). As the discontinuity moves away from the probe point, we plot the magnitude of margin to an RL mask (Y axis)—which in this case is simply 10 dB for all frequencies of interest. As such, negative values are failures, and positive values show increasing margin. Interestingly, as the discontinuity moves away from the measurement point increasing margin is gained, causing the Y value to move up. This is interesting because the discontinuity did not change in size at all; only its distance from the measurement probe changed. Hence my point that RL measures the proximity of discontinuities due to DPE with the important implication that:
- RL margin can be improved (in other words, discontinuities can be dampened,) by inserting distance or loss before a discontinuity is encountered.
So what are the colors in Figure 1? They are the size (length) of the discontinuity inserted into the surrounding 4 in. interconnect, or specifically 0.05 in., 0.1 in., 0.2 in., 0.4 in., and 0.8 in. From this variation, we learn a couple more important points:
- a small discontinuity is more easily damped, or said another way
- RL margin is harder to gain with larger discontinuities, and
- negative RL margin (leftmost in Figure 1) has more to do with the discontinuity proximity effect (DPE) than discontinuity size.
To illustrate this last point, and DPE in general, consider the system-level RL measurement in Figure 2, illustrated in blue. Looks bad, right? Indeed, it is rising above 10 dB around 4 GHz. We might immediately think “Wow, that interconnect must have lots of discontinuities.” And indeed, it does. The interconnect measured is about 35 in. long, traversing four PCBs and one cable, with a substantial number of discontinuities due to the many interconnects and connectors involved. But is the number of discontinuities the cause of the bad RL? Actually, it’s not.
Oddly enough, only one of the discontinuities in this complex interconnect causes the bad RL. And it’s not the largest discontinuity (which is a bit less than 3 in. away), but the one closest to where RL is measured. Figure 2 is an example of DPE in action. In this case, there is a non-ideal breakout route under the small BGA where the VNAs probes are placed. It’s not a terrible breakout either, just a bit of p/n asymmetry with lengths longer than the relevant feature size.1 If we remove this feature (red, removed by gating the measurement in this case), RL stays below 10 dB up to 36 GHz. Wait, fix or remove the initial 150 mil feature from a 35 in. interconnect with dozens of discontinuities and RL suddenly passes a 10 dB mask? Hard to believe, but it’s true.
So again, was the “bad” RL due to the sum of the collective set of discontinuities or the proximity of the probe to one of them? No question, it’s the latter.
- Adding Connectors: If you’re like me, you get handed a connector’s S-parameters by someone who asks, “Can we add this connector into our system?" You plot the connector’s RL and observe—by itself—that it is already at or beyond your RL mask. So, you conclude there’s no way this will work. Then, you insert it into your larger system model and mysteriously RL looks okay. Wait, doesn’t RL add like IL? No, it doesn’t. What happened? You removed the DPE, and the discontinuities in the connector that would have been unacceptable if you placed your SerDes “close” to it are now damped by the IL on either side of it.
- Minimum Lengths: Though not intuitive, many times you can tame (damp) a discontinuity by adding loss. This idea is similar to the connector example above, yet extends the concept to any troublesome discontinuity in your signal path. The solution is often to enforce a minimum route length (or loss) in front of a discontinuity to lower the DPE. This may require a mental jump because, after spending years trying to reduce length and IL, the fix here is to add it. As miniaturization brings us shorter interconnects, we’ll be doing this more and more. I have been using this technique and publishing many examples illustrating it for over a decade,2 and have a chapter devoted to the concept in my book.3
So Mid-Path Discontinuities Don't Matter?
Great question, but I’m not saying that. If you are familiar with my writings on serial links, you might be aware that I have boiled the serial link hardware development task down to resolving, if not balancing, loss and discontinuities. Well, okay, with a good dose of equalization (EQ) prowess—but that’s a firmware task. Indeed, this is the heart of my article "7 Steps to Successful Serial Links".3,4 (See Chapter 2 of Reference 3.)
If your link is loss-constrained, say at the high end of acceptable IL, you will discover that (like the system in Figure 2) your mid-path discontinuities are surprisingly well-damped and compensated, even if they are “large”. However, if your link is short—perhaps at or below the low end of acceptable IL—your link is likely reflective and under-damped. For this type of link it’s imperative to remove/fix the discontinuities, add loss, or both, because this is where the failures are.3 (See pp. 95.) So yes, mid-path discontinuities do matter—particularly in short links.
But perhaps the most substantial and non-intuitive problem with mid-path discontinuities occurs when they interact together to create a cavity resonance or discontinuity induced resonance (DIR). This occurs when energy at a frequency related to the distance between the discontinuities gets trapped and resonates enough to damage your signal integrity. This can happen both in the signal path5 and in the ground return.6,7 Please explore the published works cited to learn more about this phenomenon, and what you can do about it.
The Holy Grail of SI
For years we’ve dreamed of a metric we can apply to our channel’s S-parameters to achieve a simple “pass” or “fail” regarding signal performance—in absence of active analysis that included Tx/Rx EQ. We’ve tried ILD, ERL, and once I worked on a metric that pitted FA against IL to no avail. While COM comes close, the line between COM and active (IBIS-AMI) simulation is blurry. Indeed, it still seems a channel is best qualified by active analysis—an assertion made by PCI Express in its first revision.
Nevertheless, there’s great value in studying IL and RL to understand and manage loss and discontinuities, respectively—if you know what you’re looking at. Truth be told, though, I prefer using IL and TDR (instead of, or in addition to, RL) because TDR (impedance versus time plots) provides a direct mapping between problem and solution. Discontinuities jump out at you in TDR, because both their magnitude and position in the channel are immediately discernable.8 As such, TDR is invaluable for studying, quantifying, and improving your link’s discontinuities. TDR is available by mathematically transforming your S-Parameters into the time domain—a feature available in most SI tools.
Every day we routinely distance ourselves from various things: that loud table at the restaurant, that unsafe driver, the email that will waste our time, that opinion we disagree with. Similarly, we may need to distance our SerDes from discontinuities, due to what I have called the discontinuity proximity effect, or DPE. DPE causes excessive reflections—likely manifesting as RL mask failures. Here I’ve presented concepts and data to prod you to perceive your serial link differently. Namely that:
- discontinuities may be problematic simply because they are too close to your SerDes, and
- discontinuities, perhaps experienced as features in your RL plots, do not sum as interconnect loss elements do in your IL plots.
Please explore these concepts as you develop your next-generation serial links and post your findings in comments below. No doubt you, too, will need to damp a discontinuity to increase your link’s performance. In that light, my additional hope is that package designers pay particular heed to the concepts and data shown, because a faster SerDes in a poorly designed package (e.g., excessive discontinuities) suffers from DPE system designers cannot correct.
In this article “loss” is used as it is commonly applied in SI to refer to “insertion loss.” The idea of “insertion loss” makes more sense in other disciplines where one might be “inserting” a filter or amplifier into a circuit and quantifying the change in signal or power. In SI, we are generally not “inserting” anything, but rather quantifying the intrinsic attenuation of what is already there. Some background that might be helpful. Around the turn of the century SI simulation tools began adding support for S-parameters. It’s not that RF tools didn’t already support them, it’s just that their use and application in SI tools and tasks became imperative. And so various concepts and terminologies from RF design remain. In 2004, I held a webinar to teach SI engineers how to understand and use S-parameters, applying many parallels with the more familiar IBIS model.9 When logins passed 350, I fixed my microphone, shored up my thinking, and said to myself “Okay Telian, I don’t know if this has ever happened in SI before, but this had better be crisp.” Clearly, the GHz era had arrived. At the time, realizing it would make better sense to SI engineers, I debated revising the term “insertion loss” to “transmission loss.” Additionally, I further debated plotting loss magnitudes as linear ratios instead of decibels. Again, it’s simpler for the SI engineer to determine that a quarter of the signal remains at a certain frequency (Y axis reads 0.25) than to observe it is “12 dB down” at that frequency. But instead I chose to go with RF terminology. Maybe that was a bad choice, because I still keep my dB cheat sheet handy so I know how much a signal is attenuated—20 years later! If your SI waveform viewer lets you transform the Y axis from dB to linear, give it a try.
To reuse my simulation files, learn the specific parameters, and try or this expand this example yourself, download the DPE Project zip from the published works page of the SiGuys website. Simulate the Project using this free trial of MATLAB’s Signal Integrity Toolbox.
For more information on resolving SI in today’s high-speed serial links, be sure to read Donald Telian’s new book Signal Integrity, In Practice: A Practical Handbook for Hardware, SI, FPGA, and Layout Engineers.
- D. Telian, "Which Discontinuities are Small Enough to Ignore?" Signal Integrity Journal, April 1, 2022.
- D. Telian, S. Camerlo, B. Kirk, "Simulation Techniques for 6+ Gbps Serial Links," DesignCon, 2010, pp. 20.
- D. Telian, Signal Integrity, In Practice: A Practical Handbook for Hardware, SI, FPGA & Layout Engineers, 2021.
- D. Telian, "7 Steps to Successful Serial Links," Signal Integrity Journal, July 12, 2022.
- D. Telian, S. Camerlo, M. Steinberger, B. Katz, W. Katz, "Simulating Large Systems with Thousands of Serial Links," DesignCon, 2012, pp. 14-16.
- M. Steinberger, D. Telian, M. Tsuk, V. Iyer, J. Yanamadala, "Proper Ground Return Via Placement for 40+ Gbps Signaling," DesignCon, 2022.
- M. Steinberger, D. Telian, O. Bell, K. Rowett "Managing Differential Via Crosstalk and Ground Via Placement for 40+ Gbps Signaling," DesignCon, 2023.
- M. Steinberger, "Understanding TDR," 2012.
- D. Telian, "Webinar: Understanding and Using S-Parameters for PCB Signal Integrity," Cadence, 2004.